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C5: 0.5 µmプロセス・テクノロジ

概要
印刷バージョン
製品説明
オン・セミコンダクタのC5プロセス・ファミリは、5 Vミックスド・シグナル・アプリケーションに対して最適化されており、複雑なアナログ機能、デジタル・コンテンツ、20V動作機能を統合できる中集積度の高性能ミックスド・シグナル・テクノロジを提供します。このプロセスは、BCDプロセスの余分なマスク・ステップに要するコストなしで、専用のミックスド・シグナル0.5µmプロセスの利点を提供します。0.5 µmプロセスでは低電圧トランジスタも利用でき、低電力アプリケーションに最適です。

特長
  • 2~3層メタル・プロセス
  • ポリ-ポリ・キャパシタ
  • EEPROM
  • ショットキ・ダイオード
  • 高電圧I/O - 12/20 V
  • 高抵抗ポリ
  • 低電圧モジュール

プロセス特性

動作電圧 5、12 V
基板材料 P型、バルクまたはEPI
描画トランジスタ長 0.6 µm
ゲート酸化膜厚 13.5 nm
コンタクト/ビア・サイズ 0.5 µm
コンタクテッド・ゲート・ピッチ 3.9 µm
トップ・メタル厚 675 nm
コンタクテッド・メタル・ピッチ
メタル1 1.5 µm
メタル2、3 1.6 µm
メタル組成 TiN/AlCu/TiN

サンプル・プロセス・オプション

マスク・レイヤ*
標準CMOS、20 V拡張ドレイン付き 13/15
+ダブル・ポリ・キャパシタ 14/16
上記のすべて+1,000 Ω/square抵抗 15/17
上記のすべて+12 Vゲート 16/18
上記のすべて+低Vtデバイス 19/21
* 2メタル/3メタル

デバイス特性
(値はすべて25℃時の標準値)

高電圧トランジスタ

12 Vデュアル・ゲート・ネステッド・ドレイン
N-Ch 12 V (NU) 標準値 単位
Vt 0.95 V
Idsat 450 µA/µm
BVDSS 19 V
P-Ch 12 V (PU)
Vt -1.6 V
Idsat -110 µA/µm
BVDSS -14.5 V

20 V拡張ドレイン、15 Vゲート

N-Ch 20 V (NX) 標準値 単位
Vt 0.95 V
Idsat 400 µA/µm
BVDSS 28 V
P-Ch 20 V (PU)
Vt -1.65 V
Idsat -130 µA/µm
BVDSS -28 V

20 V拡張ドレイン、5 Vゲート
N-Ch 20 V (NT) 標準値 単位
Vt 0.75 V
Idsat 145 µA/µm
BVDSS 28 V
P-Ch 20 V (PT)
Vt -1.0 V
Idsat -55 µA/µm
BVDSS -28 V

標準トランジスタ

Nチャネル 標準値 単位
Vt 0.7 V
Idsat 450 µA/µm
Pチャネル
Vt -0.9 V
Idsat -260 µA/µm

抵抗

標準値 単位
ポリ 25 Ω/square
高信頼性ポリ 1000 Ω/square
N拡散 80 Ω/square
P拡散 110 Ω/square
Nウェル 855 Ω/square

キャパシタ

ポリ-ポリ 標準値 単位
面積 0.9 fF/µm²
周辺 0.065 fF/µm

ライブラリ
(値はすべて3.3V、25℃時の標準値)

フロントエンド・デジタル・デザイン
デジタル
合成ライブラリ
シミュレーション・ライブラリ
アナログ - 一般デザイン情報(GDI)
デザイン・ルール
SPICEモデル

デジタル・デザイン
高性能コア
4.2 kゲート/mm² *
1.58 µW/MHz/ゲート
103 psゲート遅延(2入力NAND、ファンナウト = 2)
高I/O数デザイン用トール・パッド
86 µmインライン・パッド・ピッチ
60 µmスタガード・パッド・ピッチ
558 µmパッド高さ

ミックスド・シグナル・デザイン
Cadenceテクノロジ・ファイル
Cadenceトランジスタ・ライブラリ
ミックスド・シグナル・コア
デジタル・ノイズ低減のための分離サブストレート・バス
7.4 kゲート/mm² *
0.63 µW/MHz/ゲート
558 µmパッド高さ
128 psゲート遅延(2入力NAND、ファンナウト = 2)
高ロジック・コンタクト・デザインに対するミックスド・シグナル・ショート・パッド
135 µmインライン・パッド・ピッチ
388 µmパッド高さ
ミックスド・シグナル中背パッド
86 µmインライン・パッド・ピッチ
567 µmパッド高さ
* 配線済みゲート密度

メモリ・オプション

SRAM
シングル・ポート同期型*
191 µm²/ビット(64 Kビット・メモリ)
デュアル・ポート同期型*
567 µm²/ビット(64 Kビット・メモリ)

ROM
非同期型*
14.65 µm²/ビット(64 Kビット・メモリ)
* コンパイル済み

EEPROM
NASTEE(追加ステップなしEEPROM)
ベクタ(1x4から最大1x32)
アレイ(2x4から最大32x32)


CADツールの互換性

デジタル・デザイン
Synopsys Design Compiler
Cadence Verilog

アナログ・デザイン
Cadence DFII (4.4.6)
Spectre

配置・配線
Synopsys Apollo, Astro
Cadence Silicon Ensemble

物理的検証
Mentor Calibre

詳細については、オン・セミコンダクタの販売代理店にお問い合わせください。