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MC100EP52: ECL Differential Clock/Data D Flip-Flop

Overview
Specifications
Packages
Datasheet: 3.3 V / 5 V ECL Differential Data and Clock D Flip Flop
Rev. 8 (183kB)
Product Overview
»信頼性データを表示する
»材料組成を表示
»製品変更通知 (5)
The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to VEE ) the outputs of the device will remain stable.
特長
 
  • 330ps Typical Propagation Delay
  • Maximum Frequency > 4 GHz Typical
  • PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available
アプリケーション
  • Negative edge-triggering
供給状況 & サンプル
製品
状態
Compliance
内容
外形
MSL*
梱包形態
予算 価格/Unit
タイプ
Case Outline
タイプ
数量
MC100EP52DG Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop SOIC-8 751-07 1 Tube 98 Contact Sales Office
MC100EP52DR2G Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop SOIC-8 751-07 1 Tape and Reel 2500 Contact Sales Office
MC100EP52DTG Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop TSSOP-8 948R-02 3 Tube 100 Contact Sales Office
MC100EP52DTR2G Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop TSSOP-8 948R-02 3 Tape and Reel 2500 Contact Sales Office
MC100EP52MNR4G Active
Pb-free
Halide free
ECL Differential Clock/Data D Flip-Flop DFN-8 506AA 1 Tape and Reel 1000 Contact Sales Office
面実装デバイスためのモイスチャー・レベル(260°Cリフローでの鉛フリー測定、235°Cリフローでの鉛フリー以外測定)
マーケットリードタイム(週) : 2 to 4
Arrow   (Fri Dec 09 22:03:45 MST 2016) : 511
Avnet   (2016-12-08) : <1K
Digikey   (2016-12-08) : <1K
FutureElectronics   (2016-12-08) : <1K
Mouser   (2016-12-08) : <1K
ON Semiconductor   (2016-12-07) : 12,054
マーケットリードタイム(週) : 2 to 4
ON Semiconductor   (2016-12-07) : 10,000
マーケットリードタイム(週) : 2 to 4
Arrow   (Fri Dec 09 22:03:46 MST 2016) : 2549
Digikey   (2016-12-08) : <1K
FutureElectronics   (2016-12-08) : <100
Mouser   (2016-12-08) : <1K
ON Semiconductor   (2016-12-07) : 3,700
マーケットリードタイム(週) : 2 to 4
Arrow   (Fri Dec 09 22:03:46 MST 2016) : 2340
ON Semiconductor   (2016-12-07) : 7,334
マーケットリードタイム(週) : 8 to 12
PandS   (2016-12-08) : <1K
Datasheet: 3.3 V / 5 V ECL Differential Data and Clock D Flip Flop
Rev. 8 (183kB)
Product Overview
»信頼性データを表示する
»材料組成を表示
»製品変更通知 (5)

Product Compliance Status Description Type Bits Input Level Output Level VCC Typ (V) tJitter Typ (ps) tpd Typ (ns) tsu Min (ns) th Min (ns) trec Typ (ns) tR & tF Max (ps) fToggle Typ (MHz) Package Type
Pb-free
Halide free
 Active     ECL Differential Clock/Data D Flip-Flop 
D-Type
1
CML
ECL
ECL
5
3.3
0.2
0.33
0.05
0
 
170
4000
SOIC-8
Pb-free
Halide free
 Active     ECL Differential Clock/Data D Flip-Flop 
D-Type
1
CML
ECL
ECL
5
3.3
0.2
0.33
0.05
0
 
170
4000
SOIC-8
Pb-free
Halide free
 Active     ECL Differential Clock/Data D Flip-Flop 
D-Type
1
ECL
CML
ECL
3.3
5
0.2
0.33
0.05
0
 
170
4000
TSSOP-8
Pb-free
Halide free
 Active     ECL Differential Clock/Data D Flip-Flop 
D-Type
1
ECL
CML
ECL
5
3.3
0.2
0.33
0.05
0
 
170
4000
TSSOP-8
Pb-free
Halide free
 Active     ECL Differential Clock/Data D Flip-Flop 
D-Type
1
CML
ECL
ECL
5
3.3
0.2
0.33
0.05
0
 
170
4000
DFN-8
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