MC100EP52: ECL Differential Clock/Data D Flip-Flop

Datasheet: 3.3V / 5V ECL Differential Data and Clock D Flip Flop Rev. 7 (152.0kB)	»信頼性データを表示する »材料組成を表示 »製品変更通知 (4)
Product Overview

The MC10EP/100EP52 is a differential data, differential clock D flip-flop with reset. The device is functionally equivalent to the EL52 device. Data enters the master portion of the flip-flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The differential clock inputs of the EP52 allow the device to also be used as a negative edge triggered device. The EP52 employs input clamping circuitry so that under open input conditions (pulled down to V_EE ) the outputs of the device will remain stable.

特長
330ps Typical Propagation Delay
Maximum Frequency > 4 GHz Typical
PECL Mode: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
Q Output will default LOW with inputs open or at VEE
Pb-Free Packages are Available

アプリケーション
Negative edge-triggering

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