|
|
»材料組成を表示
»No Product Change Notifications exist
|
|
|
|
|
製品説明
The NB4N111K is a differential input clock 1 to 10 HCSL fanout buffer, optimized for ultra low propagation delay variation. The NB4N111K is designed with HCSL clock distribution for FBDIMM applications in mind. Inputs can accept differential LVPECL, CML, or LVDS levels. Single-ended LVPECL, CML, LVCMOS or LVTTL levels are accepted with the proper VREFAC supply (see Figures 5, 10, 11, 12, and 13). Clock input pins incorporate an internal 50 ohm on die termination resistors.
|
特長 |
|
利点 |
| |
| |
| |
|
-
Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and400 MHz
|
|
-
Meets wide range of FBDIMM bus frequencies
|
-
<1 ps RMS Additive Clock jitter
|
|
-
Best in class for jitter performance
|
-
Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
|
|
-
Ensures operation in the majority of designs
|
-
340 ps Typical Rise and Fall Times
|
|
|
-
800 ps Typical Propagation Delay
|
|
|
-
delta tpd 100 ps Maximum Propagation Delay Variation Per Each Differential Pair
|
|
|
-
Differential HCSL Output Level
|
|
|
|
アプリケーション |
|
最終製品 |
- HCSL FBDIMM Memory CLOCK buffer
- General High Performance HCSL Fanout buffer
- Clock Distribution
- PCIe I, II, II
- Networking
- High End Computing
|
|
- Servers
- Routers
- FBDIMM Memory Card
|