feedback
このページの評価をお願いします

サポート情報をお探しですか?


NB4N11M: Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V

Overview
Specifications
Datasheet: 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator
Rev. 1 (223.0kB)
»信頼性データを表示する
»材料組成を表示
»製品変更通知 (4)
Product Overview
製品説明
The NB4N11M is a differential 1−to−2 clock/data distribution/translation chip with CML output structure, targeted for high−speed clock/data applications. The device is functionally equivalent to the EP11, LVEP11, SG11 or 7L11M devices. The device produces two identical differential output copies of clock or data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such, NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and other clock/data distribution applications.

Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS. The CML outputs are 16 mA open collector which requires resistor (RL) load path to VTT termination voltage. The open collector CML outputs must be terminated to VTT at power up. Differential outputs produces current mode logic (CML) compatible levels when receiver loaded with 50 Ω or 25 Ω loads connected to 1.8 V, 2.5 V or 3.3 V supplies. This simplifies device interface by eliminating a need for coupling capacitors.
特長
 
  • Maximum Input Clock Frequency > 2.5 GHz
  • Maximum Input Data Rate > 2.5 Gb/s
  • Typically 1 ps of RMS Clock Jitter
  • Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, RL = 25 Ω
  • 420 ps Typical Propagation Delay
  • 150 ps Typical Rise and Fall Times
  • Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V and VTT = 1.8 V to 3.6 V
  • Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP, EP, and GigaComm Devices
  • These are Pb-Free Devices
アプリケーション
  • Clock distribution in high speed networking and Automated Test Equipment.
技術資料 & デザイン・リソース
アプリケーション ノート (4) パッケージ図 (1)
シミュレーション・モデル (2) 評価ボード文書 (2)
データシート (1)  
評価/開発ツール情報
製品 状態 Compliance 簡単な説明 アクション
NB4N11MDTEVB Active
Clock/Data Input Evaluation Board
Avnet (2015-07-09) : 2
供給状況 & サンプル
製品
状態
Compliance
内容
外形
MSL*
梱包形態
予算 価格/Unit
タイプ
Case Outline
タイプ
数量
NB4N11MDTG Active
Pb-free
Halide free
Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V TSSOP-8 948R-02 3 Tube 100 Contact Sales Office
NB4N11MDTR2G Active
Pb-free
Halide free
Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V TSSOP-8 948R-02 3 Tape and Reel 2500 Contact Sales Office
面実装デバイスためのモイスチャー・レベル(260°Cリフローでの鉛フリー測定、235°Cリフローでの鉛フリー以外測定)
マーケットリードタイム(週) : 2 to 4
Avnet   (2015-07-09) : <100
Chip1Stop   (2015-07-09) : <100
Mouser   (2015-07-09) : <100
ON Semiconductor   (2015-07-08) : 13,600
PandS   (2015-07-09) : <100
マーケットリードタイム(週) : 4 to 8
PandS   (2015-07-09) : >1K
Datasheet: 3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator
Rev. 1 (223.0kB)
»信頼性データを表示する
»材料組成を表示
»製品変更通知 (4)
Product Overview

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V   Buffer   1   1:2 
 CML 
 LVCMOS 
 LVDS 
 LVPECL 
 LVTTL 
 CML   3.3   1   25   0.42   300   2500   2500   TSSOP-8 
 Pb-free 
 Halide free 
 Active     Multi Level Clock / Data Input to CML Receiver / Buffer / Translator, 2.5 Gbps, 3.3 V   Buffer   1   1:2 
 CML 
 LVCMOS 
 LVDS 
 LVPECL 
 LVTTL 
 CML   3.3   1   25   0.42   300   2500   2500   TSSOP-8 
過去に閲覧した製品
一覧をクリアする

新製品
 

NB3W800L  3.3 V, 100/133 MHz, Differential 1:8 Push-Pull Clock ZDB/Fanout Buffer for PCIe

  • Eight differential clock output Pairs @ 0.7 V
  • Meets DB800ZL performance requirements
  • Low−power NMOS push−pull HCSL compatible outputs