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NB4N316M: AnyLevel™ Input to Open Collector CML Output Buffer/ Translator w/ Input Hysteresis

Overview
Specifications
Datasheet: 3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis - 2.0 GHz Clock / 2.5 Gb/s Data
Rev. 5 (186.0kB)
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Product Overview
製品説明
The NB4N316M is a differential Clock or Data receiver and will accept AnyLevel input signals: LVPECL, CML, LVCMOS, LVTTL, or LVDS. These signals will be translated to CML, operating up to 2.0 GHz or 2.5 Gb/s, respectively. As such, the NB4N316M is ideal for SONET, GigE, Fiber Channel, Backplane and other Clock or Data distribution applications. The CML outputs are 16 mA open collector which require a resistor load path to VTT termination voltage. The open collector CML outputs must be terminated to VTT at power up. The differential outputs produce Current Mode Logic (CML) compatible levels when the receiver is loaded with 50-ohm or 25-ohm loads connected to 1.8 V, 2.5 V or 3.3 V supplies. This simplifies device interface by eliminating a need for coupling capacitors. The NB4N316M features an input threshold of approximately 25mV, providibg increased noise immunity and stability. The device is offered in a small 8-pin TSSOP package (MSOP-8 compatible).
特長
 
  • Maximum Input Clock Frequency > 2.0 GHz
  • Maximum Input Data Rate > 2.5 Gb/s
  • Typically 1 ps of RMS Clock Jitter
  • Typically 10 ps of Data Dependent Jitter
  • 550 ps Typical Propagation Delay
  • 150 ps Typical Rise and Fall Times
  • Differential Open Collector CML Outputs
アプリケーション
  • Signal interface translation for Networking and ATE
  • High Speed CLOCK Applications
技術資料 & デザイン・リソース
アプリケーション ノート (6) データシート (1)
シミュレーション・モデル (1) パッケージ図 (1)
供給状況 & サンプル
製品
状態
Compliance
内容
外形
MSL*
梱包形態
予算 価格/Unit
タイプ
Case Outline
タイプ
数量
NB4N316MDTG Active
Pb-free
Halide free
AnyLevel™ Input to Open Collector CML Output Buffer/ Translator w/ Input Hysteresis TSSOP-8 948R-02 3 Tube 100 Contact Sales Office
NB4N316MDTR2G Active
Pb-free
Halide free
AnyLevel™ Input to Open Collector CML Output Buffer/ Translator w/ Input Hysteresis TSSOP-8 948R-02 3 Tape and Reel 2500 Contact Sales Office
面実装デバイスためのモイスチャー・レベル(260°Cリフローでの鉛フリー測定、235°Cリフローでの鉛フリー以外測定)
マーケットリードタイム(週) : 8 to 12
Arrow   (Sat Jul 11 08:21:31 MST 2015) : 100
Avnet   (2015-07-09) : <1K
Chip1Stop   (2015-07-09) : <1K
Digikey   (2015-07-09) : <1K
Mouser   (2015-07-09) : <1K
マーケットリードタイム(週) : 2 to 4
Arrow   (Sat Jul 11 08:21:32 MST 2015) : 6775
ON Semiconductor   (2015-07-08) : 12,500
Datasheet: 3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis - 2.0 GHz Clock / 2.5 Gb/s Data
Rev. 5 (186.0kB)
»信頼性データを表示する
»材料組成を表示
»製品変更通知 (4)
Product Overview

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     AnyLevel™ Input to Open Collector CML Output Buffer/ Translator w/ Input Hysteresis   Signal Driver   1   1:1 
 CML 
 CMOS 
 ECL 
 HSTL 
 LVDS 
 TTL 
 CML   3.3   1   20   0.55   300   2000   2500   TSSOP-8 
 Pb-free 
 Halide free 
 Active     AnyLevel™ Input to Open Collector CML Output Buffer/ Translator w/ Input Hysteresis   Signal Driver   1   1:1 
 CML 
 CMOS 
 ECL 
 HSTL 
 LVDS 
 TTL 
 CML   3.3   1   20   0.55   300   2000   2500   TSSOP-8 
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