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NB4N527S: Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination

Overview
Specifications
Datasheet: Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination
Rev. 5 (175.0kB)
»材料組成を表示
»製品変更通知 (7)
Product Overview
製品説明
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 2.5 Gb/s or 1.25 GHz, respectively.
The NB4N527S has a wide input common mode range of GND+50 mV to VCC-50 mV combined with two 50 Ω internal termination resistors is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels without use of any additional external components.
The device is offered in a small 3 mm x 3 mm QFN-16 package. NB4N527S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements.
特長
 
  • Maximum Input Clock Frequency up to 1.25 GHz
  • Maximum Input Data Rate up to 2.5 Gb/s
  • 500 ps Maximum Propagation Delay
  • 2 ps Maximum RMS Jitter
  • 300 ps Maximum Rise/Fall Times
  • Single Power Supply; VCC = 3.3 V +/- 10%
  • Temperature Compensated TIA/EIA644 Compliant LVDS Outputs
  • Internal 50 Termination Resistor per Input Pin
  • GND + 50 mV to VCC 50 mV VCMR Range
アプリケーション
  • OC-3 to OC-48 SDH/SONET Clock & Data Applications
  • 1 GbE, 1G & 2G Fibrechannel Clock & Data Applications
  • Precision LVDS Clock Buffering & Translation
技術資料 & デザイン・リソース
アプリケーション ノート (8) パッケージ図 (1)
シミュレーション・モデル (2) 評価ボード文書 (1)
データシート (1)  
評価/開発ツール情報
製品 状態 Compliance 簡単な説明 アクション
NB4N527SMNEVB Active
Translator with Internal Termination Evaluation Board
Avnet (2015-07-09) : 4
Digikey (2015-07-09) : 2
供給状況 & サンプル
製品
状態
Compliance
内容
外形
MSL*
梱包形態
予算 価格/Unit
タイプ
Case Outline
タイプ
数量
NB4N527SMNG Active
Pb-free
Halide free
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination QFN-16 485G-01 1 Tube 123 Contact Sales Office
NB4N527SMNR2G Active
Pb-free
Halide free
Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination QFN-16 485G-01 1 Tape and Reel 3000 Contact Sales Office
面実装デバイスためのモイスチャー・レベル(260°Cリフローでの鉛フリー測定、235°Cリフローでの鉛フリー以外測定)
マーケットリードタイム(週) : 2 to 4
Avnet   (2015-07-09) : <1K
Digikey   (2015-07-09) : <1K
Mouser   (2015-07-09) : <1K
PandS   (2015-07-09) : <100
マーケットリードタイム(週) : 4 to 8
ON Semiconductor   (2015-07-08) : 3,000
Datasheet: Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination
Rev. 5 (175.0kB)
»材料組成を表示
»製品変更通知 (7)
Product Overview

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination   Signal Driver   2   1:1 
 CML 
 CMOS 
 ECL 
 HSTL 
 LVDS 
 LVDS   3.3   0.5   25   0.37   140   1500   2500   QFN-16 
 Pb-free 
 Halide free 
 Active     Translator, 3.3 V, 2.5 Gb/s Dual AnyLevel™ to LVDS Receiver/Driver/Buffer, with Internal Termination   Signal Driver   2   1:1 
 CML 
 CMOS 
 ECL 
 HSTL 
 LVDS 
 LVDS   3.3   0.5   25   0.37   140   1500   2500   QFN-16 
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