製品説明
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator capable of translating AnyLevelTM input signal (LVPECL, CML, HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance, noise immunity of the system design, and transmission line media, this device will receive, drive or translate data or clock signals up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin-for-pin plug in compatible to the SY55855V in a 3.3 V applications.
The NB4N855S has a wide input common mode range of GND + 50 mV to VCC - 50 mV. This feature is ideal for translating differential or single-ended data or clock signals to 350 mV typical LVDS output levels.
The device is offered in a small 10 lead MSOP package. NB4N855S is targeted for data, wireless and telecom applications as well as high speed logic interface where jitter and package size are main requirements.
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特長 |
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利点 |
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Guaranteed Input Clock Frequency up to 1.0 GHz
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Guaranteed Input Data Rate up to 1.5 Gb/s
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490 ps Maximum Propagation Delay
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1.0 ps Maximum RMS Jitter
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180 ps Maximum Rise/Fall Times
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Single Power Supply; VCC = 3.3 V ±10%
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Temperature Compensated TIA/EIA-644 Compliant LVDS Outputs
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GND + 50 mV to VCC - 50 mV VCMR Range
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Pb-Free Packages is Available
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アプリケーション |
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最終製品 |
- Translation of all major signal types to LVDS in heterogenous systems.
- Signal driving and reception in communications and networking applications.
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