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NB6L16: Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL

Overview
Specifications
Datasheet: Clock or Data Receiver / Driver / Translator Buffer, 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL
Rev. 8 (235.0kB)
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Product Overview
製品説明
The NB6L16 is a high precision, low power ECL differential clock or data receiver/driver/translator buffer. The device is functionally equivalent to the EL16, EP16, LVEL16 and NBSG16 devices. With output transition times of 70 ps, it is ideally suited for high frequency, low power systems. The device is targeted for Backplane buffering, GbE clock/data distribution, Fibre Channel distribution and SONET clock/data distribution applications.

Input accept LVNECL (Negative ECL), LVPECL (Positive ECL), LVTTL, LVCMOS, CML, or LVDS. Outputs are 800 mV ECL signals.
The VBB pin, an internally generated voltage supply, is available to this device only. For single−ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
特長
 
  • Input Clock Frequency 6 GHz
  • Input Data Rate Frequency 6 Gb/s
  • Low 12 mA Typical Power Supply Current
  • 70 ps Typical Rise/Fall Times
  • 130 ps Input Propagation Delay
  • On-Chip Reference for ECL Single-Ended Input - VBB Output
  • PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 with VEE = 2.375 V to 3.465 V
  • Open Input Default State
  • LVDS, LVPECL, LVNECL, LVCMOS, LVTTL and CML Input Compatible
  • Low-power Clock Buffering for Power constrained PC Add-on cards
アプリケーション
  • Backplane Data buffering
  • Signal Translation Between LVDS, CML, LVTTL or LVCMOS to LVPECL
技術資料 & デザイン・リソース
アプリケーション ノート (14) データシート (1)
シミュレーション・モデル (1) パッケージ図 (2)
供給状況 & サンプル
製品
状態
Compliance
内容
外形
MSL*
梱包形態
予算 価格/Unit
タイプ
Case Outline
タイプ
数量
NB6L16DG Active
Pb-free
Halide free
Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL SOIC-8 751-07 1 Tube 98 Contact Sales Office
NB6L16DR2G Active
Pb-free
Halide free
Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL SOIC-8 751-07 1 Tape and Reel 2500 Contact Sales Office
NB6L16DTG Active
Pb-free
Halide free
Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL TSSOP-8 948R-02 3 Tube 100 Contact Sales Office
NB6L16DTR2G Active
Pb-free
Halide free
Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL TSSOP-8 948R-02 3 Tape and Reel 2500 Contact Sales Office
面実装デバイスためのモイスチャー・レベル(260°Cリフローでの鉛フリー測定、235°Cリフローでの鉛フリー以外測定)
マーケットリードタイム(週) : 2 to 4
Arrow   (Sat Jul 11 08:21:04 MST 2015) : 55
Avnet   (2015-07-09) : <100
Digikey   (2015-07-09) : <100
FutureElectronics   (2015-07-09) : <100
Mouser   (2015-07-09) : <100
ON Semiconductor   (2015-07-08) : 1,176
PandS   (2015-07-09) : <100
マーケットリードタイム(週) : Contact Factory
マーケットリードタイム(週) : 4 to 8
Avnet   (2015-07-09) : <100
Digikey   (2015-07-09) : <100
マーケットリードタイム(週) : Contact Factory
Datasheet: Clock or Data Receiver / Driver / Translator Buffer, 2.5V / 3.3V Multilevel Input to Differential LVPECL/LVNECL
Rev. 8 (235.0kB)
»信頼性データを表示する
»材料組成を表示
»製品変更通知 (2)
GreenPoint®デザイン・ツール
Product Overview

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL    Signal Driver   1   1:1 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 ECL 
 2.5 
 3.3 
 0.2     0.13   120   6000   6000   SOIC-8 
 Pb-free 
 Halide free 
 Active     Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL    Signal Driver   1   1:1 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 ECL 
 2.5 
 3.3 
 0.2     0.13   120   6000   6000   SOIC-8 
 Pb-free 
 Halide free 
 Active     Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL    Signal Driver   1   1:1 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 ECL 
 2.5 
 3.3 
 0.2     0.13   120   6000   6000   TSSOP-8 
 Pb-free 
 Halide free 
 Active     Clock / Data Receiver / Driver / Translator Buffer, 2.5 V / 3.3 V Multilevel Input to Differential LVPECL/LVNECL    Signal Driver   1   1:1 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 ECL 
 2.5 
 3.3 
 0.2     0.13   120   6000   6000   TSSOP-8 
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