製品説明
The NB7L14M is a differential 1-to-4 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device produces two identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively.
Inputs incorporate internal 50 Ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Differential 16mA CML (Current Mode Logic) output provides matching 50 Ohm terminations, and 400 mV output swings when externally terminated, 50 Ohm to V
CC.
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特長 |
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Maximum Input Clock Frequency up to 8 GHz Typical
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Maximum Input Data Rate up to 12Gb/s Typical
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< 0.5 ps Maximum RMS Clock Jitter
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< 10 ps Data Dependant Jitter
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30 ps Typical Rise & Fall Times
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110 ps Typical Propagation Delay
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6 ps Typical Within Device Skew
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Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
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CML Output Level (400 mV Peak-to-Peak Output)Differential Output Only
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50Ω Input and Output Termination Resistors
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Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP, EP, and SG Devices
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Pb-Free Packages are Available
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アプリケーション |
- SDH/SONET OC-3 to OC-48 Data Buffering
- High Speed Precision Edge Clocking
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