| Product Description |
The ONC25 process family from ON Semiconductor is an ideal 0.25 mm low cost solution to mixed-signal designs. ONC25 is designed for 2.5, 3.3, 5.0 V single-gate or 2.5/3.3 V or 2.5/5 V dual-gate operation with high-performance/low-power and mixed-signal 2.5 V or 5.0 V digital libraries, and mixed-signal features such as MIM capacitors, Schottky diodes, zener diodes, high resistivity poly, deep Nwell for Pwell isolation and under Nwell in the digital blocks to optimize packing density. ONC25 provides the flexibility to implement a variety of mixed-signal applications.
|
| Features |
- Gate Oxide voltages: 2.5, 3.3, 5.0 V
- 2 to 5 metal layers
- Top metal option thicknesses: 1.0, 1.5, 3.0 µm
- MIM capacitor: 1.0 fF/µm² located below top metal
- Schottky diodes (planned)
- Zener diodes: 5.15, 5.5, 6.2 and 7.4 V
- High sheet resistance (1.5 kW) polysilicon resistor
- Low temperature coefficient polysilicon resistor
- Salicide process with optional blocking
- Deep Nwell for Pwell isolation, NPNs, and also may be used under Nwell in the digital blocks to optimize packing density
Process Characteristics
| Operating Voltage |
2.5, 3.3, 5 V |
| Substrate Material |
200 mm P-Type, EPI |
| Drawn Transistor Length |
0.25 µm (2.5 V CMOS) |
| Gate Oxide Thickness |
50, 70, 125 Å |
| Contact/Via Size drawn |
0.3/0.36 µm |
| Top Metal Thickness |
1.0, 1.5, and 3.0 µm |
| Contacted Metal Pitch |
| Metal 1 |
0.64 µm |
| Metal 2-5 |
0.94 µm |
| Metal Composition |
AI(0.5%Cu) |
Sample Process Options
| |
Mask Layers |
| Single gate, 2 metal |
16 |
| Dual gate, 2 metal |
22 |
| Single gate, 5 metal |
22 |
| Dual gate, 5 metal |
28 |
|
| Device Characteristics |
|
(All Values Typical at 25°C)
2.5 V Transistors
| N-Channel |
Typical Value |
Unit |
| Vt |
0.53 |
V |
| Idsat |
490 |
µA/µm |
| P-Channel |
Typical Value |
Unit |
| Vt |
-0.53 |
V |
| Idsat |
-240 |
µA/µm |
3.3 V Transistors
| N-Channel |
Typical Value |
Unit |
| Vt |
0.58 |
V |
| Idsat |
520 |
µA/µm |
| P-Channel |
Typical Value |
Unit |
| Vt |
-0.79 |
V |
| Idsat |
-265 |
µA/µm |
5.0 V Transistors
| N-Channel |
Typical Value |
Unit |
| Vt |
0.82 |
V |
| Idsat |
500 |
µA/µm |
| P-Channel |
Typical Value |
Unit |
| Vt |
-0.88 |
V |
| Idsat |
-240 |
µA/µm |
|
|
Resistors
| Resistors |
Typical Value |
Unit |
Typical Value |
Unit |
| Nwell under STI |
1400 |
Ω/square |
3600 |
ppm/°C |
| P+poly unsilicided |
280 |
Ω/square |
-75 |
ppm/°C |
| Low Tempco Poly unsilicided |
335 |
Ω/square |
-34.2 |
ppm/°C |
| High Resistance Poly unsilicided |
1500 |
Ω/square |
1200 |
ppm/°C |
Capacitors
| |
Typical Value |
Unit |
| MIM (15 V max) |
1 |
fF/µm² |
| CPNW2V (2 V gate oxide to NW) Vgs = 2.5 V |
5.28 |
fF/µm² |
| CPNW3V (3 V gate oxide to NW) Vgs = 3.0 V |
4.42 |
fF/µm² |
| CPNW5V (5 V gate oxide to NW) Vgs = 5.0 V |
2.46 |
fF/µm² |
Diodes
| |
Typical Value |
Unit |
| pimp-to-NW diode BV (1 µA/µm) |
8.07 |
V |
| Leakage (Vac=BV/2) |
0.01 |
pA |
BJT
| |
BVceo
(|Ic|=1 µA, |Ib|=1 nA) |
Beta
(|Ie|=5 µA, Vcb=0) |
| NPN |
8.2V |
15 |
| PNP |
19.3V |
2.5 |
|
|
| Libraries |
| Front-End Digital Design |
| Digital |
| Synthesis Libraries |
| Simulation Libraries |
| Analog |
| Design Rules |
| Parameterized layout cells |
| Spectre Models |
| Standard Cell |
| 5 V core cell |
| 398 total cells |
| 1-layer metal and 2-layer metal pwr rail option |
| 33.1 k gates/mm² (Routed @ 75% util) |
| 0.122 ns prop delay (2-input NAND, fanout = 2) |
| 2.5 V core cell |
| 398 total cells |
| 1-layer metal and 2-layer metal pwr rail option |
| 33.1 k gates/mm² (Routed @ 75% util) |
| 0.056 ns prop delay (2-input NAND, fanout = 2) |
|
| Memory Options |
| OTP |
| 2.5 V Poly fuse |
| 32 – 256 bit in 32 bit increments |
| 5 V Poly fuse |
| 32 – 256 bit in 32 bit increments |
|
| CAD Tool Compatibility |
| Digital Design |
| Synopsys Design Compiler |
| Cadence RTL Compiler |
| Mentor Graphics FastScan (DFT) |
| Analog/Mixed-Signal Design |
| Cadence Virtuoso, VirtuosoXL, Spectre and Eldo |
| Mentor Graphics Design Architect IC, IC Station and Eldo |
| Place and Route |
| Cadence Encounter |
| Synopsys Apollo |
| Physical Verification |
| Mentor Graphics Calibre |
|
| For more information please contact your local sales support at www.onsemi.com |
