| Product Description |
ONBCD25 from ON Semiconductor is a full-featured high-voltage 0.25 µm node technology. ONBCD25 contains 5 V single-gate or 5/12 V dual-gate high-voltage transistors combined with mixed signal features including MIM capacitors, Schottky diodes, zener diodes, high resistivity poly, plus a variety of npn/pnp bipolar transistors, capacitors, diodes and resistors. The high voltage transistors include optimized NLDMOS and high voltage PMOS 40/5 V, 40/12 V, 24/5 V and 12/12 V transistors. The high-performance/low-power 5 V digital library and one-time programmable (OTP) element offered in the baseline ONC25 technology are available as well. ONBCD25 provides the flexibility to implement a variety of mixed-signal functions in a product design.
|
| Features |
- Gate Oxide voltages: single-gate 5 V, dual-gate 5/12 V
- NLDMOS 40/5 V, 40/12 V, 24/5 V and 12/12 V (drain to source voltage/gate to source voltage)
- High voltage PMOS 40/5 V, 40/12 V, 24/5 V and 12/12 V
- High voltage Schottky diodes: 18, 30, 40 V
- Zener diodes: 5.15, 5.5, 6.2, and 7.4 V
- High voltage isolation
- Variety of npn/pnp bipolar transistors, diodes and resistors constructed with high voltage process additions
- 2 to 5 metal layers
- Top metal thickness options: 1.0, 1.5 and 3.0 µm AI-0.5% Cu
- LV MOS circuits can be floated in HV isolated wells
- MIM capacitors: 1.0 fF/mm² located below top metal
- High sheet resistance (1.5 kΩ) polysilicon resistor
- Low temperature coefficient p-type polysilicon resistor
- Salicided active and poly with optional blocking
- Characterized ESD protection cells
Process Characteristics
| Operating Voltage |
5, 12, 24, 40 V |
| Substrate Material |
200 mm P-Type, EPI |
| Drawn Transistor Length |
0.5 µm (5 V CMOS) |
| Gate Oxide Thickness |
125, 300 Å |
| Contact/Via Size |
0.3/0.36 µm |
| Top Metal Thickness |
1.0, 1.5, 3.0 µm (AI-0.5% Cu thickness) |
| Contacted Metal Pitch |
| Metal 1 |
0.64 µm |
| Metal 2-4 |
0.94 µm |
| Metal Top |
|
| 1.0 µm AI-0.5% Cu |
2.00 µm |
| 1.5 µm AI-0.5% Cu |
3.00 µm |
| 3.0 µm AI-0.5% Cu |
6.00 µm |
| Metal Composition |
AI(0.5%Cu) |
Sample Process Options
| LV MOS |
Mask Layers |
| Single gate 5 V, 2 metal |
23 |
| Single gate 5 V, 5 metal |
29 |
| Dual gate 5 V & 12 V |
+2 |
| MIM |
+1 |
| 30 V Schottky |
+1 |
| 40 V Schottky |
+1 |
| 5.15 V Zener |
+1 |
| 5.5 V Zener |
+1 |
| 1.5 kΩ/sq poly resistor |
+1 |
| LTC poly resistor |
0 to +1 |
|
| Device Characteristics |
|
(All Values Typical at 25°C)
HV DMOS
| |
Max Vds
(V) |
Typ RDS(ON)
(mΩ/mm²) |
Typ Vt
(V) |
| NLDMOS 12/12 V |
13.2 |
8.5 |
2.22 |
| PMOS 12/12 V |
25 |
58.6 |
2.34 |
PMOS 12/12 V
Low Threshold Voltage |
25 |
80.5 |
0.82 |
| NLDMOS 40/5 V |
44 |
40.8 |
0.95 |
| PMOS 40/5 V |
44 |
112 |
0.84 |
| NLDMOS 40/12 V |
44 |
44.2 |
3.24 |
| PMOS 40/12 V |
44 |
110 |
2.33 |
PMOS 40/12 V
Low Threshold Voltage |
38 |
119 |
0.83 |
| NLDMOS 24/5 V |
47.7 |
28 |
1.3 |
| PMOS 24/5 V |
33 |
60 |
0.82 |
LV MOS
| |
Typ Vt |
Typ Idsat |
| NMOS 5 V |
0.82 V |
500 µA/µm |
| PMOS 5 V |
-0.88 V |
-240 µA/µm |
Capacitors
| |
Max Voltage |
Typical Value |
| MIM |
15 V |
1.0 fFµm² |
CPNW 5 V (5 V gate oxide to NW),
Vgs=5.0 V |
5 V |
2.46 fFµm² |
Resistors
| |
Typ Value |
Temp Coef |
| Nwell under STI |
1400 Ω/sq |
3600 ppm/°C |
| P+poly unsilicided |
280 Ω/sq |
-75 ppm/°C |
| Low Tempco Poly unsilicided |
335 Ω/sq |
-34.2 ppm/°C |
| High Rs Poly unsilicided |
1500 Ω/sq |
1200 ppm/°C |
| HV NWell under STI |
690 Ω/sq |
- |
| HV PWell under STI |
4900 Ω/sq |
- |
|
|
BJTs
| |
Typ Beta |
Typ BVceo
(V) |
Typ BVcbo
(V) |
| NPNH |
52 |
26 |
65 |
| NPNL |
17.4 |
27 |
27 |
| PNPSLV |
9.3 |
24 |
35 |
| PNPS |
2.6 |
12 |
19.2 |
Forward Vf Diodes
| |
Min BV (V) |
| P+/Nwell |
7 |
| N+/Pwell |
7 |
| P+/HVnwell |
14 |
| N+/HVpwell |
14 |
| HVpwell/Nbl |
56 |
| Pwell/HVnwell |
20 |
| Pbl/Nbl |
46 |
| 18V Schottky |
22 |
| 30V Schottky |
32 |
| 40V Schottky |
44 |
Avalanche Diodes
| |
Typ BV (V) |
| Pbody/Nwell |
15 |
| 5.15 V Zener |
5.15 |
| 5.5 V Zener |
5.5 |
| 6.2 V Zener |
6.2 |
| 7.4 V Zener |
7.4 |
ESD Protection
| |
HBM Levels |
| LV ESD Diodes |
2 – 8 kV |
| LV Supply Clamps |
2 - 4 kV |
| HV 4 kV ESD Diodes |
2 - 4 kV |
| HV Supply Clamps |
2 kV |
|
|
| Libraries |
| Front-End Digital Design |
| Digital |
| Synthesis Libraries |
| Simulation Libraries |
| Analog |
| Design Rules |
| Parameterized layout cells |
| Spectre Models |
| Standard Cell |
| 5 V core cell |
| 398 total cells |
| 1-layer metal and 2-layer metal pwr rail option |
| 33.1 k gates/mm² (Routed @ 75% util) |
| 0.122 ns prop delay (2-input NAND, fanout = 2) |
|
| Memory Options |
| OTP |
| 5 V Poly fuse |
| 32 – 256 bit in 32 bit increments |
|
| CAD Tool Compatibility |
| Digital Design |
| Synopsys Design Compiler |
| Cadence RTL Compiler |
| Mentor Graphics FastScan (DFT) |
| Analog Design |
| Cadence Virtuoso, VirtuosoXL, Spectre and Eldo |
| Mentor Graphics Design Architect IC, IC Station and Eldo |
| Place and Route |
| Cadence Encounter |
| Synopsys Apollo |
| Physical Verification |
| Mentor Graphics Calibre |
|
| For more information please contact your local sales support at www.onsemi.com |
