| Product Description |
The C3/D3 process family from ON Semiconductor is an ideal 0.35 µm low cost solution to mixed-signal designs requiring a moderate amount of digital logic (up to 250 k gates). Optimized for 3.3 V operation with added devices for 5 V capability, high-performance, low-power, and mixed-signal digital libraries, and mixed-signal features such as poly-poly capacitors, Schottky diodes, and high resistivity poly. C3/D3 provides the flexibility to implement a variety of mixed-signal applications.
|
| Features |
- 3 to 5 metal layers
- Poly to poly capacitors
- Schottky diodes
- High-resistance poly
- Salicide process with optional blocking
- 5 V devices (thick gate oxide)
- 5 V tolerant I/O in normal process
Process Characteristics
| Operating Voltage |
3.3 V, 5 V |
| Substrate Material |
P-Type, EPI |
| Drawn Transistor Length |
0.35 µm |
| Gate Oxide Thickness |
7.0 nm/11.0 nm |
| Contact/Via Size |
0.4 µm/0.5 µm |
| Top Metal Thickness |
675 nm |
| Contacted Metal Pitch |
| Metal 1 |
1.1 µm |
| Metal 2-5 |
1.2 µm |
| Metal Composition |
AI/TiN |
Sample Process Options
| |
Mask Layers |
| 1 poly, 3 metal |
16 |
| 1 poly, 5 metal |
20 |
| 2 poly, 3 metal, Hi-R poly |
20 |
| 2 poly, 5 metal, Hi-R poly |
24 |
|
| Device Characteristics |
|
(All Values Typical at 25°C)
Transistors
| N-Channel |
Typical Value |
Unit |
| Vt |
0.5 |
V |
| Idsat |
510 |
µA/µm |
| P-Channel |
Typical Value |
Unit |
| Vt |
-0.554 |
V |
| Idsat |
-259 |
µA/µm |
Thick Gate Transistors
| N-Channel |
Typical Value |
Unit |
| Vt |
0.76 |
V |
| Idsat |
470 |
µA/µm |
| P-Channel |
Typical Value |
Unit |
| Vt |
-0.95 |
V |
| Idsat |
-240 |
µA/µm |
|
|
Resistors
| |
Typical Value |
Unit |
| Poly |
10 |
Ω/square |
| Hi-R Poly |
1000 |
Ω/square |
| N-Diffusion |
10 |
Ω/square |
| P-Diffusion |
10 |
Ω/square |
| N-Well |
1250 |
Ω/square |
Capacitors
| |
Typical Value |
Unit |
| Poly-Poly |
0.9 |
fF/µm² |
Diodes
| Schottky Diode |
Typical Value |
Unit |
| Area |
5.1 |
µm² |
| Id (Vf = 0.1 V) |
0.05 |
µA |
| Id (Vf = 0.3 V) |
2 |
µA |
| Id (Vf = 0.6 V) |
175 |
µA |
|
|
| Libraries |
(All values typical at 3.3 V, 25°C)
| Standard Cell |
| Ultra High Density Core Cell |
| pn sum: 2.0 |
| Area of 2-input nand (na21): 38.88 µm |
| Gate density (na21 @ 100% utilization): 25.72 k gates/mm² |
| Scan Flop density (scan flops @100% utilization): 3.215 k ff/mm² |
| Average power (@ 3.3 V): 0.604852 µW/MHz/gate |
| Mixed-Signal Core Cell – Separate substrate for reduced noise |
| pn sum: 4.5 |
| Area of 2-input nand (na21): 74.88 µm |
| Gate density (na21 @ 100% utilization): 13.35 k gates/mm² |
| Scan Flop density (scan flops @100% utilization): 1.842 k ff/mm² |
| Average power (@ 3.3 V): 0.6074 µW/MHz/gate |
| 5 V Capable Core Cell – Thick gate logic design |
| pn sum: 5.0 |
| Area of 2-input nand (na21): 108 µm² |
| Gate density (na21 @ 100% utilization): 9.259 k gates/mm² |
| Scan Flop density (scan flops @100% utilization): 1.187 k ff/mm² |
| Average power (@ 5.0 V): 3.0553 µW/MHz/gate |
| Core Cell Level Shifters |
| Bidirectional: 2 cells, pad high to core low, or pad low to core high |
| Unidirectional: 1 cell optimized for speed, pad high to core low |
| Standard I/O |
| Fat Pad I/O Library (for core limited designs) |
| 135 µm max in-line pad pitch |
| 459.15 µm pad height |
| Tall Pad I/O Library (for pad limited designs) |
| 86 µm max in-line pad pitch |
| 730 µm pad height |
| 5 V Capable I/O Library – Thick gate logic design |
| 140.40 µm max in-line pad pitch |
| 274.05 µm pad height |
|
| Memory Options |
| RAM |
| Asynchronous Single Port SRAM* |
| 35 µm²/bit (64 k bit memory) |
| Asynchronous Dual Port SRAM* |
| 64 µm²/bit (64 k bit memory) |
| ROM |
| Asynchronous Diffusion ROM* |
| 5.4 µm²/bit (64 k bit memory) |
* Compiled
| Non-Volatile Memory |
| EEPROM |
| Differential Bit Cell (Redundancy for High Reliability) |
| 2 ms Write |
| Array: up to 1 k Bits (32x32), Vector: up to 32 bits (1x32) |
| Internal Charge Pump provided |
|
| CAD Tool Compatibility |
| Digital Design |
| Synopsys Design Compiler |
| Cadence Verilog |
| Analog Design |
| Cadence DFII (4.4.6) |
| Spectre |
| Place and Route |
| Synopsys Apollo, Astro |
| Cadence Silicon Ensemble |
| Physical Verification |
| Mentor Calibre |
|
| For more information please contact your local sales support at www.onsemi.com |
