| Product Description |
Providing the density of a 0.35 µm digital process, analog/mixed-signal capability and high voltage, the Intelligent Interface Technology I3T25 process from ON Semiconductor is the answer to the need for increased digital content in a mixed-signal and/or high voltage environment. Featuring high voltage devices up to 18 V as well as digital and analog operation at 3.3 V and 12 V, the I3T25 process family features a wide range of capabilities in a single IC.
|
| Features |
- 3 to 5 metal layers
- Metal to metal (MIM) linear capacitors
- Poly to poly capacitors
- High and medium resistivity polysilicon resistors
- Floating HV thick/thin ox NDMOS andPDMOS transistors
- Floating low-voltage diodes
- Schottky diode
- Medium-voltage PNP and NPN bipolar transistors
- Zener zap diode for OTP
- Buried zener diode for clamping
- Medium-voltage floating metal capacitors
- Deep n + doped guard rings
- Medium-voltage floating metal capacitors
Process Characteristics
| Operating Voltage |
3.3, 12 V |
| Substrate Material |
N-epitaxy on P-sub, retrograde wells |
| Drawn Transistor Length |
0.35 µm |
| Gate Oxide Thickness |
7/~30 nm |
| Contact/Via Size |
0.4 µm |
| Contacted Gate Pitch |
1.3 µm |
| Top Metal Thickness |
845 nm |
| Metal Pitch |
| Metal 1 |
1.0 µm |
| Metal 2 |
1.1 µm |
| Top Metal |
1.4 µm |
| Metal Composition |
AI/Cu |
| Isolation |
LOCOS |
| ILD Planarization |
PSG/PETEOS/ +CMP |
| IMD Planarization |
PETEOS+CMP |
Sample Process Options
| |
Mask Layers |
| 3 metal, 25 V HIPO, OTP |
19 |
| 4 metal, 25 V HIPO, OTP |
21 |
| 5 metal, 25 V HIPO, OTP |
23 |
| Thick oxide |
+3 |
| Poly Poly Cap |
+1 |
| MIMC |
+1 |
|
| Device Characteristics |
|
(All Values Typical at 25°C)
Low-Voltage Transistors
| NMOS Transistor |
Typical
Value |
Unit |
| Vt
(10/0.35,
linear extrapolated) |
0.59 |
V |
| Vmax=Vbd |
3.6 |
V |
| IDS
(10/0.35,
Vds=Vgs=3.3 V) |
530 |
µA/µm |
| PMOS Transistor |
| Vt
(10/0.35, linear extrapolated) |
-0.57 |
V |
| Vmax=Vbd |
-3.6 |
V |
IDS
(10/0.35, Vds=Vgs=3.3 V) |
-250 |
µA/µm |
Thick Oxide High-Voltage Transistors (Extended Drain)
| Floating NDMOS (18 V) |
Typical
Value |
Unit |
| Vt (Vd=0.1 V) |
1.3 |
V |
| Vbd (Vgs = 0) |
31 |
V |
| Vgsmax |
12 |
V |
| Vdsmax, SOA*
(Vgs=Vgsmax, full lifetime) |
12 |
V |
| Vdsmax (Vgs
full lifetime) |
18 |
V |
| Ron*Area
(Vg=18 V, Vd=0.5 V) |
27 |
mΩ*mm² |
| Ids |
260 |
µA/µm |
| Floating PDMOS (18 V) |
| Vt (Vd=0.1 V) |
-1.3 |
V |
| Vbd (Vgs = 0) |
-35 |
V |
| Vgsmax |
-12 |
V |
| Vdsmax, SOA*
(Vgs=Vgsmax, full lifetime) |
-12 |
V |
| Vdsmax (Vgs
full lifetime) |
-18 |
V |
| Ron*Area
(Vg=18 V, Vd=0.5 V) |
71 |
mΩ*mm² |
| Ids |
-110 |
µA/µm |
* Symmetric Device Available.
Diodes
Zener Diode:
PBZD (a=2 μm) |
Typical
Value |
Unit |
| Vz @ 100 µA |
4.6 |
V |
| Rzener |
45 |
Ω |
| Ileak @ Vz=0.5 V |
200 |
nA |
| Zapping Zener Diode
for OTP: UZZD |
| Vz @ 1 µA |
1.5 |
V |
| Vbd @ 10 mA |
4.5 |
V |
| Ileak @ Vz= 1 V |
1.4 |
V |
| Poly Diode for
Gate Clamping: POLYD |
| Vreverse @ Ia=10 µA |
6.8 |
V |
| Schottky |
|
|
| Vbd @ 1 µA |
15 |
V |
| ILeak @ 5.5 |
<20 |
nA |
Capacitors (Parameter @ 25°C)
| Type (Maximum Voltage) |
Typical
Value |
Unit |
Metal2/Metal2.5 Plate:
MIMC (3.6V) |
1.5 |
fF/µm² |
| Poly Poly Capacitor (13.2V) |
1 |
fF/µm² |
Resistors (Parameter @ 25°C)
| Resistor Type |
Typical
Value |
Unit |
| High-Resistance Poly: HIPO |
975 |
Ω/square |
| Salicided P+ Poly: LOPOR |
2.4 |
Ω/square |
| Unsalicided P+ Poly: PPOLR |
240 |
Ω/square |
| Unsalicided P+ in Mwell |
64 |
Ω/square |
| Unsalicided N+ Poly: NPOLR |
292 |
Ω/square |
| Unsalicided N+ in Pwell |
47.5 |
Ω/square |
| Nwell under FOX (field oxide) |
958 |
Ω/square |
| Nwell in AA (active area) |
800 |
Ω/square |
| Pwell in AA (active area) |
1755 |
Ω/square |
|
|
Thin Oxide High-Voltage Transistors (Extended Drain)
| Floating NDMOS |
Typical
Value |
Unit |
| Vt (Vd=0.1 V) |
0.6 |
V |
| Vbd (Vgs = 0) |
31 |
V |
| Vgsmax |
3.6 |
V |
| Vdsmax, SOA*
(Vgs=Vgsmax, full lifetime) |
12 |
V |
| Vdsmax (Vgs
full lifetime) |
18 |
V |
| Ron*Area
(Vg=3.3 V, Vd=0.5 V) |
35 |
mΩ*mm² |
| Ids |
280 |
µA/µm |
| Floating PDMOS |
| Vt (Vd=0.1 V) |
-0.6 |
V |
| Vbd (Vgs = 0) |
-28 |
V |
| Vgsmax |
-3.6 |
V |
| Vdsmax, SOA*
(Vgs=Vgsmax, full lifetime) |
-12 |
V |
| Vdsmax (Vgs
full lifetime) |
-18 |
V |
| Ron*Area
(Vg=3.3 V, Vd=0.5 V) |
75 |
mΩ*mm² |
| Ids |
-121.5 |
µA/µm |
Thick Oxide High-Voltage Transistors (Nested Drain)
| Floating NDMOS (12 V) |
Typical
Value |
Unit |
| Vt (Vd=0.1 V) |
1.3 |
V |
| Vbd (Vgs = 0) |
21 |
V |
| Vgsmax |
12 |
V |
| Vdsmax, SOA* (Vgs=Vgsmax, full lifetime) |
8 |
V |
| Vdsmax (Vgs
full lifetime) |
12 |
V |
| Ron*Area (Vg=18 V, Vd=0.5 V) |
15 |
mΩ*mm² |
| Ids |
260 |
µA/µm |
| Floating PDMOS (12 V) |
| Vt (Vd=0.1 V) |
-1.4 |
V |
| Vbd (Vgs = 0) |
-21 |
V |
| Vgsmax |
-12 |
V |
| Vdsmax, SOA*
(Vgs=Vgsmax, full lifetime) |
-8 |
V |
| Vdsmax (Vgs
full lifetime) |
-12 |
V |
| Ron*Area
(Vg=18 V, Vd=0.5 V) |
75 |
mΩ*mm² |
| Ids |
-92 |
µA/µm |
* Symmetric Device Available.
Bipolar Transistors
| Bipolar Transistors Vertical Low-Voltage NPN (Parameter, E_area=3.61 µm²) |
Typical
Value |
Unit |
| Hfe @ Ic=10 µA |
17.3 |
- |
| Bvceo @ Ic=1 µA |
20.5 |
V |
| Bvces @ Ic=1 µA |
20.9 |
V |
Vertical Low-Voltage PNP Transistor
(Parameter, E_area=0.64 µm²) |
| Hfe @ Ic=10 µA |
20.1 |
- |
| Bvceo @ Ic=1 µA |
-14.5 |
V |
| Bvces @ Ic=1 µA |
-19.5 |
V |
|
|
| Libraries |
(All values typical at 25°C)
| Standard Cell |
| Ultra High Density Core Cell |
| pn sum: 2.0 |
| Area of 2-input nand (na21): 38.88 µm² |
| Gate density (na21 @ 100% utilization): 25.72 k gates/mm² |
| Scan Flop density (scan flops @100% utilization): 3.215 k ff/mm² |
| Average power (@ 3.3 V): 0.2929 µW/MHz/gate |
| Core Cell Level Shifters |
| Unidirectional: 1 cell optimized for speed, pad high to core low |
| Standard I/O |
| Fat Pad I/O Library (for core limited designs) |
| 172.80 µm min in-line pad pitch |
| 180.00 µm pad height |
| Tall Pad I/O Library (for pad limited designs) |
| 86 µm min in-line pad pitch |
| 322.50 µm pad height |
|
| Memory Options |
| RAM |
| Synchronous High Speed/High Temp Single Port SRAM |
| Minimum: 16 words x 2 bits |
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …) |
| Synchronous High Speed/High Temp Dual Port SRAM |
| Minimum: 16 words x 2 bits |
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …) |
| Low Power Synchronous SRAM |
| Minimum: 64 words x 4 bits |
Maximum: 128 k bits
(ie: 16 k words x 8 bits, 8 k words x 16 bits, …) |
| ROM |
| Synchronous High Speed/High Temp Diffusion ROM |
| Minimum: 256 words x 4 bits |
Maximum: 512 k bits
(ie: 64 k words x 8 bits, 32 k words x 16 bits, …) |
| Low Power Synchronous Via Programmable ROM |
| Minimum: 256 words x 4 bits |
Maximum: 512 k bits
(ie: 64 k words x 8 bits, 32 k words x 16 bits, …) |
| Non-Volatile Memory |
| OTP – One Time Programmable |
| Fuse: Zener Diode optimized for low power zapping |
| Both Serial and Parallel Output Capability |
| In field programming available |
| Vector: Up to 320 bits |
| EEPROM – No additional masks or processing steps |
| Differential Bit Cell (Redundancy for High Reliability) |
| 2ms Write/Erase |
| Array: up to 8 k bits (128x64), Vector: 8 to 64 bits (1x8 to 1x64) |
| Internal Charge Pump provided |
| Memory Failure Rate: <10ppm, <1ppm with ECC (128x56) |
| Automotive qualification AEC-Q100 |
|
| CAD Tool Compatibility |
| Digital Design |
| Synopsys Design Compiler |
| Cadence Verilog |
| Analog Design |
| Cadence DFII (4.4.6) |
| Cadence Spectre |
| Place and Route |
| Synopsys Apollo |
| Cadence Silicon Ensemble |
| Physical Verification |
| Mentor Graphics Calibre |
|
| For more information please contact your local sales support at www.onsemi.com |
