Arithmetic Functions | MC100LVEL33

3.3 V ECL ÷·4 ディバイダ

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MC100LVEL33 は統合 4 分周ディバイダです。LVEL は機能的に EL33 と同等で、3.3 V 電源で動作します。リセット・ピンは非同期で、立ち上がりエッジでアサートされます。電源起動時、内部フリップフロップはランダム状態に達します。リセットによりシステム内の複数の LVEL33 の同期が可能です。内部的に生成された電圧源である VBB ピンは、このデバイスでのみ使用できます。シングルエンド入力状態では、使用されていない差動入力は、スイッチング・リファレンス電圧として VBB に接続されます。 また、VBB に AC 結合入力を再バイアスさせることもできます。使用する場合は、0.01 F キャパシタを介して VBB と VCC の結合を解除し、電流のソースまたはシンクを 0.5 mA に制限します。使用しない場合、 VBB は必ずオープンのままにします。

  • Phase-Locked Loops
  • 630ps Propagation Delay
  • 4.0 GHz Typical Maximum Frequency
  • ESD Protection: >4 KV HBM, >200 V MM
  • The 100 Series Contains Temperature Compensation
  • PECL Mode Operating Range: VCC= 3.0 V to 3.8 V with VEE= 0 V
  • NECL Mode Operating Range: VCC= 0 V with VEE= -3.0 V to -3.8 V
  • Internal Input Pulldown Resistors
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1
    For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 130 devices
  • Pb-Free Packages are Available

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

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Type

Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

tpd Typ (ns)

tR & tF Max (ps)

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MC100LVEL33DG

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CAD Model

Pb

A

H

P

SOIC-8

751-07

1

260

TUBE

98

Y

Divider

LVDS

ECL

3.3

4000

0.67

320

Price N/A

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MC100LVEL33DR2G

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CAD Model

Pb

A

H

P

SOIC-8

751-07

1

260

REEL

2500

Y

Divider

LVDS

ECL

3.3

4000

0.67

320

Price N/A

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MC100LVEL33DTG

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CAD Model

Pb

A

H

P

TSSOP-8

948R-02

3

260

TUBE

100

Y

Divider

LVDS

ECL

3.3

4000

0.67

320

Price N/A

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MC100LVEL33DTR2G

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Active

CAD Model

Pb

A

H

P

TSSOP-8

948R-02

3

260

REEL

2500

Y

Divider

LVDS

ECL

3.3

4000

0.67

320

Price N/A

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