Drivers & Fanout Buffers | NB3F8L3005C

2

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Datasheet
CAD Model

CAD Model

Overview

NB3F8L3005C は、3.3 V / 2.5 V コア VDD と、2 つのフレキシブル 3.3 V / 2.5 V / 1.8 V / 1.5 V VDDOx 電源で動作する 2:1:5 クロック/データ・ファンアウト・バッファで、VDD 以下でなければなりません。Mux は、クリスタル入力、または差動/SE クロック/データ入力から選択します。差動入力は、LVPECL、LVDS、HCSL、または SSTL およびシングルエンド・レベルを受け入れます。MUX 制御ライン SEL は、表 3 に従って、 CLK/CLK、またはクリスタル入力ピンを選択します。クロック入力が選択されると、クリスタル入力は無効になります。出力イネーブル・ピン OE は、表 4 に従って Low の場合、高インピーダンス状態 (Hi-Z) を同期的に強制します。出力は、5 つのシングルエンド LVCMOS 出力で構成されます。

  • Clock Distribution
  • Networking and Communications
  • High End Computing
  • Wireless and Wired Infrastructure
  • Switch/Routers
  • Servers
  • Test and Measurement
  • Automated Test Equipment
  • Five LVCMOS / LVTTL Outputs up to 200 MHz
  • Differential Inputs Accept LVPECL, LVDS, HCSL, SSTL, orLVCMOS/LVTTL
  • Crystal Interface
  • Crystal Input Frequency Range: 10 MHz to 50 MHz
  • Output Skew: 10 ps Typical
  • Additive RMS Phase Jitter @ 156.25 MHz, (12 kHz – 20 MHz):0.03 ps (Typical)
  • Synchronous Output Enable
  • Output Defined Level When Input is Floating
  • Multiple Power Supply Modes Available (See Datasheet)
  • Two Separate Output Bank Power Supplies
  • Industrial Temperature Range: −40°C to 85°C

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Type

Channels

Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

Reference Price

NB3F8L3005CMNTBG

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Active

CAD Model

Pb

A

H

P

QFN-24

485DJ

1

260

REEL

1000

Y

Buffer

1

2:1:5

SSTL

LVTTL

3.3

0.03

25

~NA~

600

200

~NA~

Price N/A

More Details

NB3F8L3005CMNTXG

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Active

CAD Model

Pb

A

H

P

QFN-24

485DJ

1

260

REEL

3000

Y

Buffer

1

2:1:5

SSTL

LVTTL

3.3

0.03

25

~NA~

600

200

~NA~

Price N/A

More Details

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