NB3L208KMNGEVB: 1:8 HCSL Fanout Buffer Evaluation Board

The NB3L208KMNGEVB evaluation board is designed to test and evaluate the NB3L208K, which is a differential 1:8 Clock fanout buffer with High-speed Current Steering Logic (HCSL) outputs. Inputs can directly accept differential LVPECL, LVDS and HCSL signals. Single-ended LVPECL, HCSL, LVCMOS, or LVTTL levels are accepted with a proper external VTH reference supply. These signals will be translated to HCSL and eight identical copies of Clock will be distributed, operating up to 350 MHz.
製品 状態 Compliance 簡単な説明 使用パーツ アクション
1:8 HCSL Fanout Buffer Evaluation Board NB3L208KMNG
タイプ ドキュメント・タイトル ドキュメント ID/サイズ 修正
Eval Board: Manual NB3L208K Evaluation Board User's Manual EVBUM2295/D - 424 KB  1 

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