Clock/Data Input Evaluation Board

Overview



The NB6L611 is a differential 1:2 clock or data fanout buffer. The differential inputs incorporate internal 50-ohm termination resistors that are accessed through the VTD pins and will accept LVPECL, CML, LVDS, LVCMOS or LVTTL logic levels. The VREFAC pin is an internally generated voltage supply available to this device only. VREFAC is used as a reference voltage for single-ended PECL or NECL inputs. For all single-ended input conditions, the unused complementary differential input is connected to VREFAC as a switching reference voltage. VREFAC may also rebias capacitor-coupled inputs. When used, decouple VREFAC with a 0.01uF capacitor and limit current sourcing or sinking to 0.5mA. When not used, VREFAC output should be left open. The device is housed in a small 3mm x 3mm 16-pin QFN package. The NB6L611 is a member of the ECLinPS MAX family of high performance clock and data management products.

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Clock/Data Input Evaluation Board

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技術文書

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EVBUM2190/D

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Eval Board: Manual

635.9 KB

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Eval Board: Manual

December 01, 2019

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