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/Title (NB3L208K - 2.5V, 3.3V Differential 1:8 HCSL Fanout Buffer)
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BroadVision, Inc.
2020-11-03T09:19:41+01:00
2017-10-11T14:08:56-07:00
2020-11-03T09:19:41+01:00
application/pdf
NB3L208K - 2.5V, 3.3V Differential 1:8 HCSL Fanout Buffer
ON Semiconductor
Description
The NB3L208K is a differential 1:8 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides eight
identical copies operating up to 350 MHz.
The NB3L208K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB800H
compliant. As such, system designers can take advantage of the
NB3L208K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475 resistor from
IREF (Pin 27) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
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