Power Modes

RSL15 has three main power modes: Run Mode, Sleep Mode, and Standby Mode. Run Mode is the default functional mode. Sleep Mode and Standby Mode power down and/or reconfigure subsystems to achieve lower system-level power consumption; they are generally categorized as Low Power Modes.

An overview of the power modes and operating modes is shown in the "Power Modes" table. States and configurability of subsystems in each power mode are summarized in the "Power Mode Subsystems" table.

Table: Power Modes

Power Mode

Description

Run Mode

Processor, RF subsystem, and memory are powered as needed by the user application – clocks are active, all peripherals available.

Idle mode, a subset of run mode, configures the system as though entering standby mode, where the Arm Cortex-M33 processor is held waiting for an interrupt or event instead of actually entering standby mode.

Sleep Mode

The lowest power mode. Processor and RF subsystem are powered down and not clocked. Only selected wakeup sources are powered. Memory retention (and amount of memory retained) is optional. Some peripherals are available in Sleep Mode. On wakeup, the ROM restores the system before program execution begins.

Smart Sense Mode is a subset of Sleep Mode, highlighted by the use of the ultra low power data acquisition subsystem in a configuration that spans both Sleep and Run Modes.

Deep Sleep mode is another sub-set of Sleep Mode, with further limitations on wakeup sources and no memory retention. It offers the lowest power consumption.

Standby Mode

A low power mode with faster wakeup time than Sleep Mode. Processor and RF subsystem are powered with lower voltage and not clocked. Only selected wakeup sources are powered. Memory retention (and amount of memory retained) is configurable. Some peripherals are available in Standby Mode. On wakeup, the program execution is resumed (i.e., the instruction right after the LWFI statement is executed).
Table: Power Mode Subsystems

Sub-Blocks

Power Modes

 

 

Run Mode

Sleep Mode

Standby Mode

 

 

 

 

Core

 

 

 

 

Arm Cortex-M33 Processor

Clock, normal voltage

No clock, low voltage or OFF

No clock, low voltage

Arm Cortex-M33 Processor FPU

Clock, normal voltage or OFF

No clock, low voltage or OFF

No clock, low voltage or OFF

Arm Cortex-M33 Processor Debug

Clock, normal voltage or OFF

No clock, low voltage or OFF

No clock, low voltage or OFF

Baseband

Clock, normal voltage or OFF

No clock, low voltage or OFF

No clock, low voltage or OFF

Baseband timer

Clock, normal voltage

Clock, low voltage or No clock, OFF

Clock, low voltage

Arm CryptoCell-312 (+ its memories)

Clock, normal voltage or OFF

No clock, low voltage or OFF

No clock, low voltage or OFF

Arm CryptoCell-312 Always On

Clock, normal voltage

No clock, low voltage or OFF

No clock, low voltage

Individual RAM instances

Clock, normal voltage or OFF

No clock, low voltage retention mode or OFF

No clock, low voltage retention mode

Flash instance

Clock, normal voltage or OFF

No clock, OFF

No clock, low voltage, OFF

 

ACS

 

Analog registers

Active

Active

Active

Wakeup GPIOs

SW programmable

SW programmable

SW programmable

RTC clock

SW programmable

SW programmable

SW programmable

 

 

 

 

 

 

 

 

Analog

 

 

 

 

 

 

 

 

 

 

Bandgap

ON

SW programmable

ON

VCC regulator

ON

SW programmable

ON

VDDC regulator

Normal voltage

OFF

Low voltage

VDDM regulator

Normal voltage

OFF

Low voltage

VDDC retention regulator

SW programmable

SW programmable

SW programmable

VDDM retention regulator

SW programmable

SW programmable

SW programmable

VDDCP charge pump

ON

SW programmable

ON

VDDFLASH regulator

ON

OFF

SW programmable

RF regulator

SW programmable

OFF

SW programmable

PA regulator

SW programmable

OFF

SW programmable

Temp sensor

SW programmable

OFF

OFF

Current source

SW programmable

OFF

OFF

LSAD

ON

OFF

OFF

Ultra Low Power (ULP) Data Acquisition Subsystem

SW programmable

SW programmable

SW programmable

SAR-ADC

SW programmable

SW programmable

SW programmable

RF front-end

SW programmable

OFF

SW programmable

SDAC

SW programmable

OFF

OFF

ACOMP

SW programmable

SW programmable

SW programmable

RF

RF front-end

SW programmable

OFF

SW programmable

NOTE: The power modes in descending order of power consumption are Run, Idle, Standby, Smart Sense, and Sleep.

Keeping the Debugger Connected in Low Power Modes

If the Arm Cortex-M33-Debug power domain remains active, and a debug connection has been previously established to the device, the debug link will remain active across different power modes. This allows the device to be debugged while in Sleep or Standby Mode.

To support debugging in Sleep and Standby Modes, the following items are forced to remain enabled during these modes:

  • VDDC and VDDM regulators

  • Pads used by the debug port, by masking pad retention configuration for only the active debug port pads (in SW debug mode this includes only the SWCLK and SWDIO pads, in JTAG debug mode this includes JTCK, JTMS, JTDI, JTDO, and optionally JTRESET).

IMPORTANT: The device will consume more power when a debug connection is used than the device would consume if the debug connection is not used.

NOTE: To maintain the same behavior as when the debug port is disabled in Sleep or Standby Mode, VDDC will be reset if the ACS_VDDRET_CTRL_VDDCRET_ENABLE bit from the ACS_VDDRET_CTRL register is not set. As it is not possible to match the VDDM behavior between cases where debug is enabled and debug is not enabled in Sleep and Standby Modes, take extra care in applications to appropriately set the ACS_VDDRET_CTRL_VDDMRET_ENABLE bit from the ACS_VDDRET_CTRL register if the contents of any RAM instances are to be retained when the debug port is disabled.

Run Mode

In Run Mode, all the circuitry is powered on.

Idle Mode

Idle Mode is a subset of the Run Mode configurations, allowing for some power savings relative to Run Mode, with the fastest wakeup time of any power mode. In Idle Mode, the device is configured as though entering into Standby Mode, but rather than disabling the system and isolating memories, the Arm Cortex-M33 processor is held waiting for an interrupt or event instead of actually entering Standby Mode, to minimize the time needed to return to normal Run Mode execution.

Sleep Mode

When operating in Sleep Mode, RSL15 shows very low current consumption. Only the wakeup logic (through pad, RTC, or sensor interface) is kept powered. The regulators, RF block, etc., are disabled. The bandgap, digital core, and memories can be optionally powered, at low voltage.

If the digital core is not powered (i.e., the core retention regulator is not enabled), a reset is generated when entering Sleep Mode, and all registers in the digital core are reset to their default values. Registers in the Analog Control Sub-system (ACS) always keep their values over power mode cycles.

The ACS_BOOT_CFG_PADS_RETENTION_EN bit in the ACS_BOOT_CFG register needs to be set prior to entering Sleep Mode, in cases where VDDC and VDDM are not powered during this mode. This ensures that the pads keep their configuration (direction, state, etc.) during sleep time. Upon wakeup, the boot PROM code is executed. The initial pad configuration (the one used before entering the Sleep Mode) needs to be restored by the software before resetting the PADS_RETENTION_EN bit, to avoid toggling the pads.

The RF block (the analog section of the RF block) can be disconnected from its supply through the ACS_VDDRF_CTRL register. The RF (the digital section of the RF block) and Baseband, CryptoCell, CM33-FPU, and CM33-Debug power domains can be powered down through the SYSCTRL_RF_POWER_CFG, SYSCTRL_CRYPTOCELL_PWR_CFG, SYSCTRL_FPU_PWR_CFG, and SYSCTRL_DBG_PWR_CFG registers, respectively.

The following wakeup sources are typically selected using the configuration registers of the ACS:

  1. Wakeup through an external event on the GPIO[3:0] pads
  2. Wakeup through an ACOMP event
  3. Wakeup through the baseband timer
  4. Wakeup through the RTC, clocked either by the internal 32 kHz RC oscillator or the 32 kHz XTAL oscillator. The sleep time can be programmed using the RTC configuration registers of the ACS (see Real Time Clock (RTC)).
  5. Wakeup through a Sensor interface threshold event or FIFO full event.

Entering Sleep Mode starts the following sequence:

  1. The system clock is stopped.
  2. Reset is asserted unless the VDDC retention regulator is enabled.
  3. All memories (flash, PROM and RAM) are isolated from the core (AND gates).
  4. Memories are powered off. However, if the VDDM retention regulator is enabled, RAM instances enabled in the memory enable retention latches are put into retention mode.
  5. The logic is disconnected from its supply unless the core retention regulator is enabled.
  6. The baseband timer is disconnected from its supply unless the VDDT power switch is enabled; to do this, short VDDT to VDDC when VDDCRET is enabled, or to VDDACS when VDDCRET is disabled.
  7. The RF block is disconnected from its supplies. Note that the RF block needs to be isolated manually if the VDDC retention regulator is enabled.

  8. The charge pump, VDDC, VDDM, and VDDRF regulators are disabled.

NOTE: To keep the charge pump enabled during Sleep Mode, set the ACS_SLEEP_MODE_CFG_VDDCP_ENABLE bit of the ACS_SLEEP_MODE_CFG register.

  1. The VCC regulator converter is disabled.

NOTE: To keep the bandgap enabled during Sleep Mode, set the ACS_SLEEP_MODE_CFG_BG_ENABLE bit of the ACS_SLEEP_MODE_CFG register.

  1. The bandgap is disabled.

NOTE: To keep the bandgap enabled during Sleep Mode, set the ACS_SLEEP_MODE_CFG_BG_ENABLE bit of the ACS_SLEEP_MODE_CFG register.

At wakeup, the following sequence restarts the system:

  1. Eight LSBs of the RTC counter are captured in the ACS_WAKEUP_STATE_RTC_VALUE bit field of the ACS_WAKEUP_STATE register, to record the wakeup time.
  2. The bandgap is enabled.
  3. The other regulators are set according to the configuration registers when VDDC and VDDM are ready.
  4. Memories are powered back on when VDDM is ready.
  5. The wakeup delay is applied.
  6. Memory isolation is removed.
  7. The system clock is enabled.
  8. The digital reset is released, enabling boot PROM execution, unless the core retention regulator has been enabled.

Smart Sense Mode

Smart Sense Mode is a low power features that can work as a subset of the Sleep Mode configurations. Smart Sense takes advantage of the low power capability of Sleep Mode, while keeping some digital and analog peripherals, including the ultra low power (ULP) data acquisition subsystem, active with minimal processor intervention. Smart Sense allows an RSL15 device not only to remain responsive to external events, but also to monitor and acquire data from external sensors with very low system-level power consumption. Typical wakeup sources used with Smart Sense Mode include the analog comparitor (ACOMP) (see Analog Comparator) and the FIFO (FIFO_FULL) and threshold (THRESHOLD) sources from the ultra low power data acquisition subsystem (see Ultra-Low Power Data Acquisition Subsystem). If you are using Smart Sense Mode, we recommend configuring the ULP data acquisition subsystem to be clocked from STANDBYCLK for consistent data collection in both Run Mode and Smart Sense Mode.

Deep Sleep Mode

The Deep Sleep Mode is a subset of Sleep Mode and offers the lowest power consumption. Every block except the VDDACS regulator, the ACS, the CryptoCell-312 always-on, and the analog comparator (ACOMP) are powered down. The Arm CryptoCell-312 and the ACOMP can be programmed to be powered on or off during Deep Sleep Mode.

In this mode, the ACS does not receive a clock and there is no option for core or memory retention.

The RSL15 device supports the following wakeup sources in Deep Sleep Mode:

  • GPIO[3:0] pad
  • Analog comparator

NOTE: VDDCRET must always be disabled before entering Deep Sleep Mode by clearing the ACS_VDDRET_CTRL_VDDCRET_ENABLE bit in the ACS_VDDRET_CTRL register.

Standby Mode

Standby Mode can be used to reduce the average power consumption for short intervals of inactivity. In this mode, the logic and memories are not clocked, and are powered at a reduced voltage to minimize the leakage current. The ACS, bandgap, and digital regulator are active in this mode.

Most of the blocks can be powered down individually using memory-mapped registers.

The RF block (the analog section of the RF block) can be disconnected from its supply through the ACS_VDDRF_CTRL register. The RF (the digital section of the RF block) and Baseband, CryptoCell, CM33-FPU, and CM33-Debug power domains can be powered down through the SYSCTRL_RF_POWER_CFG, SYSCTRL_CRYPTOCELL_PWR_CFG, SYSCTRL_FPU_PWR_CFG, and SYSCTRL_DBG_PWR_CFG registers, respectively.

The reduced voltage level can be programmed in the STANDBY_VTRIM field of the ACS_VDDC_CTRL and ACS_VDDM_CTRL registers. (See Power Supply Registers.

Entering Standby Mode starts the following sequence:

  1. The system clock is stopped.
  2. All memories (flash, PROM and RAM) are isolated from the core (AND gates).
  3. ROM and flash are powered off, and the relevant RAM instances are placed in retention mode.
  4. The VDDC and VDDM regulators’ output voltages are set to their standby voltages.

At wakeup, the following sequence restarts the system:

  1. Eight LSBs of the RTC counter are captured in the ACS_WAKEUP_STATE_RTC_VALUE field of the ACS_WAKEUP_STATE register, to record the wakeup time.
  2. The VDDC and VDDM regulator output voltages are set to the normal voltage.
  3. Memories are powered back on.
  4. The wakeup delay is applied.
  5. Memory isolation is removed.
  6. Clock is enabled and system execution is resumed.

Entering a Low Power Mode

NOTE: Wakeup event flags must be cleared before entering any Low Power Mode. If the application does not do this, and if a wakeup event flag is still set, the system wakes up immediately. These flags are not reset by the core watchdog reset. (See Power Modes.)

Entering any of the Low Power Modes is performed with these steps:

  1. For Sleep Mode, if custom boot is selected in the ACS_BOOT_CFG_BOOT_SELECT field of the ACS_BOOT_CFG register, store the desired memory access configuration in the ACS_BOOT_GP_DATA register.
  2. Enable the wakeup source if needed. For example, the GPIO[3:0] wakeup source can be enabled by setting the relevant ACS_WAKEUP_CFG_GPIO*_EN and ACS_WAKEUP_CFG_GPIO*_POL bits in the ACS_WAKEUP_CFG register. RTC alarm wakeup source can be enabled by configuring and enabling it through the ACS_RTC_CFG and ACS_RTC_CTRL registers (Real Time Clock (RTC)). Using the baseband timer as a wakeup source requires configuring the baseband controller registers.
  3. Set an appropriate value of wakeup delay in the ACS_WAKEUP_CFG_DELAY field of the ACS_WAKEUP_CFG register.
  4. Clear all sticky wakeup event flags in the ACS_WAKEUP_CTRL register. If this is not done, and if a wakeup event flag is still set, the system wakes up immediately.
  5. For Sleep Mode, if the logic content is to be kept, set the ACS_VDDRET_CTRL_VDDCRET_ENABLE bit in the ACS_VDDRET_CTRL register (see Section 1.1.3 “Power Supply Registers” on page 1).
  6. For Sleep Mode, if RAM content is to be kept, set the ACS_VDDRET_CTRL_VDDMRET_ENABLE bit in the ACS_VDDRET_CTRL register, and configure the RAM instances to be kept in retention mode in the SYSCTRL_MEM_POWER_STARTUP and SYSCTRL_MEM_POWER_ENABLE registers (see Memory  Registers).
  7. For Sleep Mode, put the pads in retention mode by setting the ACS_BOOT_CFG_PADS_RETENTION_EN bit in the ACS_BOOT_CFG register.
  8. For Sleep Mode, if the baseband low power timer is kept powered, enable the ACS_VDDRET_CTRL_VDDTRET_EN bit in the ACS_VDDRET_CTRL register (see Section 1.1.3 “Power Supply Registers” on page 1).
  9. For Sleep Mode, if the Arm CryptoCell-312 Always On is kept powered, enable the ACS_PWR_CTRL_CCAO_PWR_EN bit in the ACS_PWR_CTRL register.
  10. For Sleep Mode, if the ULP data acquisition subsystem is kept powered, enable the ACS_PWR_CTRL_SENSOR_PWR_EN bit in the ACS_PWR_CTRL register.
  11. Switch the SYSCLK to the RC oscillator by setting the ACS_RCOSC_CTRL_RC_FSEL field of the ACS_RCOSC_CTRL register to RC_OSC_3MHZ. If the RC oscillator is calibrated for a frequency different from 3 MHz, clear the ACS_RCOSC_CTRL_RC_FTRIM_FLAG field of the ACS_RCOSC_CTRL register, as it must be correct for the boot ROM.
  12. For Standby Mode, including Smart Sense Mode, if the RFCLK needs to stay active (typically when the standby period is very short), leave the oscillator enabled and set the RFCLK clock divider in the RF block to Disabled (i.e., no clock output). If the RFCLK does not need to stay active (typically when the standby period is longer), disable it; it restarts after coming out of Standby Mode.
  13. When entering Sleep Mode with the digital logic in retention (VDDCRET enabled), ensure that the RF is isolated (access bit disabled).
  14. Write the relevant 32-bit power-down key in the ACS_PWR_MODES_CTRL register.
  15. Put the CPU in power down mode with the WFI statement. This is required for entering all Low Power Modes.

IMPORTANT: The ACS waits for the Arm Cortex-M33 processor to enter into a WFI state before starting to enter into a low power mode. This has two potential impacts:

  • If an interrupt is pending when the processor reaches the WFI instruction, the processor will not enter a WFI state and does not enter a low power mode. Execution will continue with the instruction following the WFI statement.

  • If no interrupt is pending when the processor reaches the WFI instruction, the processor will enter a WFI state. The ACS then takes 4.5 system clock cycles to enter into a low power mode. Due to this delay, a race condition results if an interrupt occurs during the first three cycles of this process, while the digital logic and memories are being placed into retention. If an interrupt occurs during this process, the Arm Cortex-M33 processor resumes, and if this interrupt occurred in the first three cycles there is a danger that the processor might access a powered down memory prior to going to a low power mode (if the interrupt occurs in the fourth cycle, the processor does not have sufficient time to execute any instructions before transitioning to the low power mode).

    If this race condition is triggered it can cause either a bus or memory fault, or an access to a partially powered down memory which would cause a corrupted memory access. To avoid this potential fault condition, follow the WFI instruction with at least three cycles of dummy operations that can be safely accessed while memories remain in retention, and which do not count on any data read for proper operation (as shown in the supplied firmware and sample code).

IMPORTANT: In the firmware sample code, the values defined by TWOSC (in the app.h file) is used to configure the time required for analog wake-up, 48 MHz XTAL oscillator stabilization, and execution of software wakeup functions. Those values (in microseconds) are based on use of the RSL15 EVBs, SDK sample code, and room temperature. You might need to tune the TWOSC value based on your system capacitance, characteristics of the 48 MHz XTAL oscillator, wakeup function execution time, sleep duration, and operating temperatures.

Waking Up from a Low Power Mode

If an event occurs on any selected wakeup source while the system is entering a Low Power Mode, the system wakes up immediately.

After wakeup, by reading the ACS_WAKEUP_CTRL register, the Arm Cortex-M33 processor knows which event source has wakened the device up. (See Wakeup Sourcesfor a list of wakeup sources.) In case another event occurs during the wakeup sequence, multiple wakeup source bits can be set when the ACS_WAKEUP_CTRL register is read. The read-only ACS_WAKEUP_STATE_WAKEUP_SRC field from the ACS_WAKEUP_STATE register indicates the first wakeup source that actually wakes up the system.

The ACS_BOOT_CFG register contains the ACS_BOOT_CFG_BOOT_SELECT field which, when configured to BOOT_FLASH_XTAL_DEFAULT_TRIM or BOOT_FLASH_XTAL_CUSTOM_TRIM by the software, tells the system (handled by the system booting software) to enable the RF block and start the 48 MHz XTAL oscillator directly after boot. This can reduce the boot time considerably, as the 48 MHz XTAL oscillator can have a long start-up time.

The ACS_BOOT_CFG_BOOT_SELECT field of the ACS_BOOT_CFG register, when configured to BOOT_CUSTOM by the software, tells the system (handled by the system booting software) to execute the code from the flash or RAM using information stored in a RAM instance that has been kept in retention. The VDDM retention regulator must be enabled to keep content of the RAM instance valid on wakeup. For details on how the wakeup from retention memory works, see Memory Instances.

The remaining ACS_BOOT_CFG_BOOT_SELECT configuration is BOOT_FLASH_XTAL_DISABLE, which does not configure the 48 MHz XTAL oscillator, and boots the system like the first boot.

The ACS_BOOT_CFG register contains the ACS_BOOT_CFG_BOOT_ROT_BYPASS bit. If this bit is set, the boot ROM skips the Root of Trust procedure when coming out of a Low Power Mode. This bit then needs to be reset by writing 0 to it.

Finally, the ACS_BOOT_CFG register contains the ACS_BOOT_CFG_BOOT_PWR_CAL_BYPASS bit. If this bit is set, the boot ROM skips the calibration of the analog part when coming out of a Low Power Mode. The bit then needs to be reset by writing 0 to it.

The ACS_WAKEUP_CFG_DELAY field in the ACS_WAKEUP_CFG register defines a delay from the point when VDDC and VDDM are ready to the point when the digital reset is released; this delay ensures that VDDC and VDDM have sufficient time to settle into a safe operating voltage before full wakeup.

IMPORTANT: For proper operation, the ACS_WAKEUP_CFG_DELAY field in the ACS_WAKEUP_CFG register must be set to a minimum delay of WAKEUP_DELAY_2.

Wakeup Sources

The following are the wakeup sources that can wake RSL15 from a Low Power Mode:

  • GPIO[3:0] pad
  • Baseband timer
  • RTC timer alarm, RTC clock tick, and RTC overflow errors
  • DC-DC overload
  • Analog comparator
  • ULP data acquisition subsystem FIFO full
  • ULP data acquisition subsystem threshold