The NLA9555 device provides 16 bits of General Purpose parallel Input/Output(GPIO) expansion through the I2Cbus/SMBus. The NLA9555 consists of two 8-bit Configuration (Input or Output selection). Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers. At power on, all I/Os default to inputs. Each I/O may be configured as either input or output by writing to its corresponding I/O configuration bit. The data for each Input or Output is kept in its corresponding Input or Output register. The Polarity Inversion register may be used to invert the polarity of the read register. All registers can be read by the system controller. The NLA9555 provides an open drain interrupt output which is activated when any input state differs from its corresponding input port register state. The interrupt output is used to indicate to the system controller that an input state has changed. The power on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (AD0, AD1, AD2) are used to configure the I2Cbus target address of the device. Up to 64 of these devices in any combination may share the same I2Cbus/SMBus.
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