Drivers & Fanout Buffers | MC100LVEP14

2.5 V / 3.3 V 1

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製品

Overview

MC100LVEP14 は低スキュー 1:5 差動ドライバで、クロック分散を念頭に置いて設計され、2 つのクロック・ソースを 1 つの入力マルチプレクサで受け付けます。ECL/PECL 入力信号は、差動またはシングルエンド (VBB 出力が使用されている場合) のどちらかです。HSTL 入力は、LVEP14 が PECL 条件下で動作しているときに使用できます。

  • 100 ps Device-to-Device Skew
  • 25 ps Within Device Skew
  • 400 ps Typical Propagation Delay
  • Maximum Frequency > 2 GHz Typical
  • PECL and HSTL Mode: VCC = 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • LVDS Input Compatible
  • Open Input Default State

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CAD Models

Compliance

Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

Container Qty.

ON Target

Type

Channels

Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

Reference Price

MC100LVEP14DTG

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Active

CAD Model

Pb

A

H

P

TSSOP-20

9.48

1

260

TUBE

75

N

Buffer

1

2:1:5

CML

ECL

HSTL

LVDS

ECL

3.3

0.181

25

0.4

225

2000

-

Price N/A

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MC100LVEP14DTR2G

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Active

CAD Model

Pb

A

H

P

TSSOP-20

9.48

1

260

REEL

2500

Y

Buffer

1

2:1:5

CML

ECL

HSTL

LVDS

ECL

3.3

0.181

25

0.4

225

2000

-

Price N/A

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信頼性データ

Die Related Summary Data

Device: MC100LVEP14DTG

Equivalent to wafer fab process: MOSAIC

製品技術

製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

MOSAIC

0

476668904

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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