Drivers & Fanout Buffers | NB3N853501E

入力 Mux - 2

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Overview

NB3N853501E3 は、低スキュー 3.3 V 電源 2:1:4 クロック分散ファンアウト・バッファです。入力 MUX は、LVCMOS/LVTTL レベルを使用して、CLK_SEL (CLK1 には HIGH、CLK0 には LOW) ピンにより 2 つの LVCMOS/LVTTL CLK ラインから 1 つ選びます。CLK_EN ピンは、LVCMOS/LVTTL レベル (出力を有効にするには HIGH、出力を無効にするには LOW) を使用して、出力を同期的に有効または無効にして、ラント・パルスを除去します。

  • Teleconmmunications
  • Networking
  • Computing Systems
  • SONET/SDH

  • LAN/WAN
  • Enterprise Servers
  • ATE
  • Test and Measurement

  • Four differential LVPECL Outputs
  • Two Selectable LVCMOS/LVTTL CLOCK Inputs
  • Up to 266 MHz Clock Operation
  • Output to Output Skew: 30 ps
  • Device to Device Skew 250 ps (Max.)
  • Propagation Delay 1.9 ns (Max.)
  • Operating range: VCC = 3.3 5% V( 3.135 to 3.465 V)
  • Additive Phase Jitter, RMS: 0.023 ps (Typ)
  • Industrial Temp. Range (40C to 85C)

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Input / Output Ratio

Input Level

Output Level

VCC Typ (V)

tJitterRMS Typ (ps)

tskew(o-o) Max (ps)

tpd Typ (ns)

tR & tF Max (ps)

fmaxClock Typ (MHz)

fmaxData Typ (Mbps)

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NB3N853501EDTR2G

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CAD Model

Pb

A

H

P

TSSOP-20

9.48

1

260

REEL

2500

Y

Buffer

1

2:1:4

LVCMOS

LVTTL

LVPECL

3.3

0.062

30

-

700

266

~NA~

Price N/A

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Die Related Summary Data

Device: NB3N853501EDTR2G

Equivalent to wafer fab process: ONC25

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等価デバイス時間

MTBF/MTTF (時間)

FITS

ONC25

1

2712519294

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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