Skew Management | MC100EP196

3.3 V ECL プログラマブル遅延チップ

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Overview

MC100EP196 は、主にクロックのスキュー調整とタイミング調整用に設計されたプログラマブル遅延チップ (PDC) です。差動 ECL 入力信号のプログラム可能な可変遅延を提供します。EP195 と同様のアーキテクチャで、FTUNE ピンを使用して遅延をさらに調整できる機能が追加されています。FTUNE 入力は、VCC から VEE までのアナログ電圧を取り、出力遅延を 0 〜 60 ps に微調整します。

  • Maximum Frequency > 1.2 GHz Typical
  • PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
  • Open Input Default State
  • Safety Clamp on Inputs
  • A Logic High on the ENbar Pin Will Force Q to Logic Low
  • D[0:10] Can Accept Either ECL, LVCMOS, or LVTTL Inputs
  • VBB Output Reference Voltage
  • Pb-Free Packages are Available

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Package Type

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MSL Type

MSL Temp (°C)

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Input Level

Output Level

VCC Typ (V)

fMax Typ (MHz)

td(prog) Min (ns)

td(prog) Max (ns)

td(step) Typ (ps)

tJitter Typ (ps)

tR & tF Max (ps)

Reference Price

MC100EP196FAG

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CAD Model

Pb

A

H

P

LQFP-32

561AB

2

260

JTRAY

250

Y

CML

ECL

ECL

3.3

1200

8.6

12

11

3

200

Price N/A

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MC100EP196FAR2G

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Active

CAD Model

Pb

A

H

P

LQFP-32

561AB

2

260

REEL

2000

Y

CML

ECL

ECL

3.3

1200

8.6

12

11

3

200

Price N/A

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信頼性データ

Die Related Summary Data

Device: MC100EP196FAG

Equivalent to wafer fab process: MOSAIC

製品技術

製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

MOSAIC

0

476668904

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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