位相ロック・ループ高性能シリコン・ゲート CMOS

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Overview

技術資料および設計リソース データ・シート (1) パッケージ図面 (1)

  • Output Drive Capability: 10 LSTTL Loads
  • Low Power Consumption Characteristic of CMOS Devices
  • Operating Speeds Similar to LSTTL
  • Wide Operating Voltage Range for VCO: 3.0 to 6.0 V
  • Low Input Current: 1.0 A Maximum (except SIGIN and COMPIN)
  • In Compliance with the Requirements Defined by JEDEC StandardNo. 7 A
  • Low Quiescent Current: 80 A Maximum (VCO disabled)
  • High Noise Immunity Characteristic of CMOS Devices
  • Diode Protection on All Inputs
  • Chip Complexity: 279 FETs or 70 Equivalent Gates

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MC74HC4046BDTR2G

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H

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TSSOP-16

1

260

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2500

N

CMOS

CMOS

3

6

50

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