Zero Delay Buffers | NB3W800L

PCIe 用の 3.3 V 100/133 MHz 差動 1

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Overview

NB3W800L は、DB800ZL 仕様のすべてのパフォーマンス要件を満たす低電力の 8 出力差動バッファです。NB3W800L は、Intel® QuickPath インターコネクト (Intel QPI & UPI)、PCIe Gen1/Gen2/Gen3/Gen4、SAS、SATA、および Intel スケーラブル・メモリ・インターコネクト (Intel SMI) アプリケーションのリファレンス・クロックを配布できます。固定の内部フィードバック・パスにより、重要な QPI アプリケーションの低ドリフトが維持されます。

  • Industrial
  • Networking
  • Computing
  • Consumer
  • PCIe Gen 1, Gen 2, Gen 3, Gen 4

  • Desktop
  • Notebook
  • Switches / Routers
  • Servers
  • Automated Test Equipment

  • 8 Differential Clock Output Pairs @ 0.7 V
  • Low−power NMOS Push−pull HCSL Compatible Outputs
  • Output−to−output Skew <50 ps
  • Input−to−output Delay Variation <100 ps
  • PCIe Phase Jitter: Gen3 <1.0 ps RMS, Gen4 <0.5ps RMS
  • QPI 9.6GT/s 12UI Phase Jitter <0.2 ps RMS
  • Individual OE Control; Hardware Control of Each Output
  • PLL Configurable for PLL Mode or Bypass Mode (Fanout Operation)
  • 100 MHz or 133 MHz PLL Mode Operation; Supports PCIe Gen 1, Gen 2, Gen 3, Gen 4, and QPI & UPI Applications
  • Selectable PLL Bandwidth; Minimizes Jitter Peaking in Downstream PLL’s
  • Spread Spectrum Compatible; Tracks Input Clock Spreading for Low EMI
  • SMBus Programmable Configurations

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NB3W800LMNTXG

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CAD Model

Pb

A

H

P

QFN-48

485DP

3

260

REEL

2500

Y

HCSL

HCSL

8

3.3

50

133.33

50

Price N/A

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信頼性データ

Die Related Summary Data

Device: NB3W800LMNTXG

Equivalent to wafer fab process: ONC18

製品技術

製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

ONC18

2

6465777234

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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