Buffers | MC74HC125A

クアッド非反転バッファ、3 ステート

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Overview

高性能シリコンゲート CMOS。MC74HC125A および MC74HC126A のピンアウトは LS125 および LS126 と同等です。入力は標準 CMOS 出力に準拠、プルアップ抵抗器があれば LSTTL 出力に準拠します。 HC125A および HC126A 非反転バッファは、3 ステート・メモリ・アドレス・ドライバ、クロックドライバ、その他のバス指向システムと使用するように設計されています。デバイスには、アクティブロー (HC125A) またはアクティブハイ (HC126A) の 4 つの別個の出力イネーブルがあります。

  • Output Drive Capability: 15 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 mA
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the Requirements Defined by JEDEC Standard No. 7A
  • Chip Complexity: 72 FETs or 18 Equivalent Gates
  • Pb-Free Packages are Available

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MC74HC125ADG

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CAD Model

Pb

A

H

P

SOIC-14

751A-03

1

260

TUBE

55

N

4

3-State

2

6

24

6

$0.1576

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MC74HC125ADR2G

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CAD Model

Pb

A

H

P

SOIC-14

751A-03

1

260

REEL

2500

N

4

3-State

2

6

24

6

$0.1167

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MC74HC125ADTG

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CAD Model

Pb

A

H

P

TSSOP-14 WB

948G

1

260

TUBE

96

N

4

3-State

2

6

24

6

$0.2456

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MC74HC125ADTR2G

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CAD Model

Pb

A

H

P

TSSOP-14 WB

948G

1

260

REEL

2500

N

4

3-State

2

6

24

6

$0.1477

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Die Related Summary Data

Device: MC74HC125ADG

Equivalent to wafer fab process: CMOS SUB

製品技術

製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

CMOS SUB

2

920154574

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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