Latches & Registers | MC74HC595A

シフト・レジスタ 3 ステート

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高性能シリコンゲート CMOS MC74HC595A を構成するのは、8 ビットのシフト・レジスタと 8 ビットの D タイプ・ラッチ、3 ステート並行出力です。シフト・レジスタはシリアル・データを受信し、シリアル出力を送出します。シフト・レジスタはパラレル・データも 8 ビット・ラッチへ送出します。シフト・レジスタとラッチのクロック入力はそれぞれ独立しています。シフト・レジスタの非同期リセットもあります。HC595A は SPI シリアル・データ・ポートと CMOS MPU/MCU 上で直接インタフェースします。

  • This product is general usage and suitable for many different applications.

  • *Standard Device (No Specific End Product)

  • Output Drive Capability: 15 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 mA
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the Requirements Defined by JEDEC Standard No. 7A
  • Chip Complexity: 328 FETs or 82 Equivalent Gates
  • Improvements over HC595
    Improved Propagation Delays
    50% Lower Quiescent Power
    Improved Input Noise and Latchup Immunity
  • Pb-Free Packages are Available*

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MC74HC595ADG

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SOIC-16

751B-05

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260

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48

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MC74HC595ADR2G

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MC74HC595ADR2G-Q

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MC74HC595ADTG

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948F-01

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$0.1952

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MC74HC595ADTR2G

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MC74HC595ADTR2G-Q

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MC74HC595AMN1TWG-Q

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QFN-16

485AW

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3000

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NLV74HC595ADG

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Die Related Summary Data

Device: MC74HC595ADG

Equivalent to wafer fab process: CMOS SUB

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等価デバイス時間

MTBF/MTTF (時間)

FITS

CMOS SUB

2

920154574

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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