Logic Gates | MC14012B

デュアル 4 入力 NAND ゲート

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Overview

これらのデュアル 4 入力 NAND ゲートは、シングル・モノリシック構造 (相補型 MOS) の P/N チャネル・エンハンスメントモード・デバイスによって構築されています。主な利用目的は、低電力消費および/または高ノイズ耐量です。

  • Supply Voltage Range = 3.0 Vdc to 18 Vdc
  • All Outputs Buffered
  • Capable of Driving Two Low-power TTL Loads or One Low-power Schottky TTL Load Over the Rated Temperature Range.
  • Double Diode Protection on All Inputs
  • Pin-for-Pin Replacements for Corresponding CD4000 Series B Suffix Devices
  • Pb-Free Packages are Available*

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Package Type

Case Outline

MSL Type

MSL Temp (°C)

Container Type

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ON Target

Type

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VCC Min (V)

VCC Max (V)

tpd Max (ns)

IO Max (mA)

Reference Price

MC14012BDG

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Active

CAD Model

Pb

A

H

P

SOIC-14

751A-03

1

260

TUBE

55

N

NAND

2

3

18

130

null

$0.1847

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MC14012BDR2G

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Active

CAD Model

Pb

A

H

P

SOIC-14

751A-03

1

260

REEL

2500

N

NAND

2

3

18

130

null

$0.1847

More Details

NLV14012BDG

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Obsolete

CAD Model

Pb

A

H

P

SOIC-14

751A-03

1

260

TUBE

55

N

NAND

2

3

18

null

null

Price N/A

More Details

NLV14012BDR2G

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Active

CAD Model

Pb

A

H

P

SOIC-14

751A-03

1

260

REEL

2500

N

NAND

2

3

18

null

null

$0.1741

More Details

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信頼性データ

Die Related Summary Data

Device: MC14012BDG

Equivalent to wafer fab process: CMOS STD

製品技術

製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

CMOS STD

3

3597164517

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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