Multiplexers | MC74HC157A

データ・セレクタ / マルチプレクサ (Mux)、2 入力 Q

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高性能シリコン・ゲート CMOS。MC74HC157A のピンアウトは LS157 と同等です。入力は標準 CMOS 出力に準拠、プルアップ抵抗器があれば LSTTL 出力に準拠します。 このデバイスは、2 つのニブル (A または B) を、選択入力によって決定された単一のポート (Y) にルーティングします。データは非反転形式で出力に表示されます。出力イネーブル入力のハイ・レベルは、4 つの Y 出力すべてをロー・レベルに設定します。

  • Output Drive Capability: 10 LSTTL Loads
  • Outputs Directly Interface to CMOS, NMOS, and TTL
  • Operating Voltage Range: 2.0 to 6.0 V
  • Low Input Current: 1.0 mA
  • High Noise Immunity Characteristic of CMOS Devices
  • In Compliance with the Requirements Defined by JEDEC Standard No. 7A
  • Chip Complexity: 82 FETs or 20.5 Equivalent Gates
  • Pb-Free Packages are Available*

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MC74HC157ADG

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

TUBE

48

N

4

2

6

21

6

$0.198

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MC74HC157ADR2G

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

REEL

2500

N

4

2

6

21

6

$0.1283

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MC74HC157ADR2G-Q

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CAD Model

Pb

A

H

P

SOIC-16

751B-05

1

260

REEL

2500

F

4

2

6

21

6

$0.198

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MC74HC157ADTR2G

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CAD Model

Pb

A

H

P

TSSOP-16

948F-01

1

260

REEL

2500

N

4

2

6

21

6

$0.1283

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MC74HC157ADTR2G-Q

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Active

CAD Model

Pb

A

H

P

TSSOP-16

948F-01

1

260

REEL

2500

F

4

2

6

21

6

$0.1757

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Die Related Summary Data

Device: MC74HC157ADG

Equivalent to wafer fab process: CMOS SUB

製品技術

製品技術

等価デバイス時間

MTBF/MTTF (時間)

FITS

CMOS SUB

2

920154574

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Re-calculate Data

Data is based on the following assumptions.

Note: The temperature and confidence level may be adjusted to your requirements.

Disclaimer: A reliability FIT rate calculated using this tool shall not be used for any functional safety purpose. In case a raw FIT rate needs to be estimated for a component which is targeted to be used in a safety critical application (i.e. compliant to ISO 26262 standard) it should be calculated according to generic safety standards (IEC62380, IEC61709, SN29500, FIDES, etc.)

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