SYSCTRL_MEM_POWER_ENABLE
|
Bit Field |
Read/Write |
Field Name |
Description |
|---|---|---|---|
|
17:16 |
RW |
BB_DRAM_ENABLE |
Baseband DRAM[1:0] power enable control |
|
15:8 |
RW |
DRAM_ENABLE |
DRAM[7:0] power enable control |
|
1 |
RW |
FLASH_ENABLE |
Flash[0:0] power enable control |
|
0 |
RW |
PROM_ENABLE |
PROM power enable control |
|
Bit Field |
Field Name |
Value Symbol |
Value Description |
Hex Value |
|---|---|---|---|---|
|
17:16 |
BB_DRAM_ENABLE |
BB_DRAM0_POWER_DISABLE |
Baseband DRAM0 disabled |
0x0* |
|
|
|
BB_DRAM1_POWER_DISABLE |
Baseband DRAM1 disabled |
0x0* |
|
|
|
BB_DRAM0_POWER_ENABLE |
Baseband DRAM0 enabled |
0x1 |
|
|
|
BB_DRAM1_POWER_ENABLE |
Baseband DRAM1 enabled |
0x2 |
|
15:8 |
DRAM_ENABLE |
DRAM0_POWER_DISABLE |
DRAM0 disabled |
0x0 |
|
|
|
DRAM1_POWER_DISABLE |
DRAM1 disabled |
0x0 |
|
|
|
DRAM2_POWER_DISABLE |
DRAM2 disabled |
0x0 |
|
|
|
DRAM3_POWER_DISABLE |
DRAM3 disabled |
0x0 |
|
|
|
DRAM4_POWER_DISABLE |
DRAM4 disabled |
0x0 |
|
|
|
DRAM5_POWER_DISABLE |
DRAM5 disabled |
0x0 |
|
|
|
DRAM6_POWER_DISABLE |
DRAM6 disabled |
0x0 |
|
|
|
DRAM7_POWER_DISABLE |
DRAM7 disabled |
0x0 |
|
|
|
DRAM0_POWER_ENABLE |
DRAM0 enabled |
0x1* |
|
|
|
DRAM1_POWER_ENABLE |
DRAM1 enabled |
0x2 |
|
|
|
DRAM2_POWER_ENABLE |
DRAM2 enabled |
0x4 |
|
|
|
DRAM3_POWER_ENABLE |
DRAM3 enabled |
0x8 |
|
|
|
DRAM4_POWER_ENABLE |
DRAM4 enabled |
0x10 |
|
|
|
DRAM5_POWER_ENABLE |
DRAM5 enabled |
0x20 |
|
|
|
DRAM6_POWER_ENABLE |
DRAM6 enabled |
0x40 |
|
|
|
DRAM7_POWER_ENABLE |
DRAM7 enabled |
0x80 |
|
1 |
FLASH_ENABLE |
FLASH0_POWER_DISABLE |
FLASH0 disabled |
0x0* |
|
|
|
FLASH0_POWER_ENABLE |
FLASH0 enabled |
0x1 |
|
0 |
PROM_ENABLE |
PROM_POWER_DISABLE |
PROM disabled |
0x0 |
|
|
|
PROM_POWER_ENABLE |
PROM enabled |
0x1* |