*$ *========================================================== * Opamp Model * * These models were developed by: * AEI Systems, LLC * 5933 W. Century Blvd. Suite 1100 * Los Angeles, California 90045 * Copyright 2011, all rights reserved. * * This model is subject to change without notice. * Users may not directly or indirectly re-sell or * re-distribute this model. This model may not * be used, modified, or altered * without the consent of AEi Systems. * * For more information regarding modeling services, * model libraries and simulation products, please * call AEi Systems at (310) 216-1144, or contact * AEi by email: info@aeng.com. http://www.AENG.com * * $Revision: 4.0a $ * $Author: C.E. HYMOWITZ $ * $Date: 1 April 2007 04:31:07 $ *========================================================== *$ .SUBCKT LMV331 1 2 3 4 5 * | | | | | * | | | | Output * | | | Negative Supply * | | Positive Supply * | Inverting Input * Non-inverting Input * * * The following ICs are covered by this model: * LMV331/393/339 * * Date of model creation: 9-13-2012_3:22:26_PM * * Revision History: * REV A: 07-Sep-12, Initial Input * * Recommendations: * Use PSPICE (or SPICE 2G6; other simulators may require translation) * For a quick, effective design, use a combination of: data sheet * specs, bench testing, and simulations with this macromodel * For high impedance circuits, set GMIN=100F in the .OPTIONS statement * * Supported: * Typical performance for temperature range (-40 to 125) degrees Celsius * DC, AC, Transient, and Noise analyses. * Most specs, including: offsets, DC PSRR, DC CMRR, input impedance, * open loop gain, voltage ranges, supply current, ... , etc. * Temperature effects for Ibias, Iquiescent, Iout short circuit * current, Vsat on both rails, Slew Rate vs. Temp and P.S. * * Not Supported: * Some Variation in specs vs. Power Supply Voltage * Vos distribution, Ib distribution for Monte Carlo * Distortion (detailed non-linear behavior) * Some Temperature analysis * Process variation * Behavior outside normal operating region * * Input Stage V10 3 10 -450M R10 10 11 690K R11 10 12 690K G10 10 11 10 11 144U G11 10 12 10 12 144U C11 11 12 11.5E-15 C12 1 0 1.00P E12 71 14 POLY(6) 20 0 21 0 22 0 23 0 26 0 27 0 2.5M 86.2 86.2 86.2 86.2 1 1 G12 1 0 62 0 1m G13 1 2 63 0 1u M12 11 14 15 15 NMI M14 12 2 15 15 NMI G14 2 0 62 0 1m C14 2 0 1.00P I15 15 4 50.0U V16 16 4 -250M GD16 16 1 TABLE {V(16,1)} ((-100,-1.00P)(0,0)(1m,1u)(2m,1m)) V13 3 13 -250M GD13 2 13 TABLE {V(2,13)} ((-100,-1.00P)(0,0)(1m,1u)(2m,1m)) R71 1 0 1.00E12 R72 2 0 1.00E12 R73 1 2 1.00E12 *C13 1 2 1.00E-15 * * Noise, PSRR, and CMRR I20 21 20 423U D20 20 0 DN1 D21 0 21 DN1 I22 22 23 1N R22 22 0 1k R23 0 23 1k G26 0 26 POLY(2) 3 0 4 0 0.00 -316U -316U R26 26 0 1 G27 0 27 POLY(2) 1 0 2 0 -2.50M 158U 158U R27 27 0 1 * * Open Loop Gain, Slew Rate G30 0 30 12 11 1 R30 30 0 1.00K G31 0 31 3 4 21.8 I31 0 31 DC 3.39 R31 31 0 1 TC=0.00,0.00 GD31 30 0 TABLE {V(30,31)} ((-100,-1n)(0,0)(1m,0.1)(2m,2)) G32 32 0 3 4 101 I32 32 0 DC 156 R32 32 0 1 TC=0.00,0.00 GD32 0 30 TABLE {V(30,32)} ((-2m,2)(-1m,0.1)(0,0)(100,-1n)) G33 0 33 30 0 1m R33 33 0 1K G34 0 34 33 0 50.1M R34 34 0 1K C34 34 0 265N G37 0 37 34 0 1m R37 37 0 1K C37 37 0 159E-15 G38 0 38 37 0 1m R38 39 0 1K L38 38 39 159N E38 35 0 38 0 1 G35 33 0 TABLE {V(35,3)} ((-1,-1n)(0,0)(6.5,1n))(7.15,1)) G36 33 0 TABLE {V(35,4)} ((-7.15,-1)((-6.5,-1n)(0,0)(1,1n)) * * Output Stage R80 50 0 100MEG G50 0 50 57 96 2 R58 57 96 0.50 R57 57 0 100 C58 5 0 2.00P G57 0 57 POLY(3) 3 0 4 0 35 0 0 3.75M 5.00M 10.0M GD55 55 57 TABLE {V(55,57)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) GD56 57 56 TABLE {V(57,56)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) E55 55 0 POLY(2) 3 0 51 0 0.00 1 -100K E56 56 0 POLY(2) 4 0 52 0 0.00 1 -10.0M R51 51 0 1k R52 52 0 1k GD51 50 51 TABLE {V(50,51)} ((-10,-1n)(0,0)(1m,1m)(2m,1)) GD52 50 52 TABLE {V(50,52)} ((-2m,-1)(-1m,-1m)(0,0)(10,1n)) G53 3 0 POLY(1) 51 0 -50.0U 1M G54 0 4 POLY(1) 52 0 -50.0U -1M * * Current Limit G99 96 5 99 0 1 R98 0 98 1 TC=0.00,0.00 G97 0 98 TABLE { V(96,5) } ((-10.0,-23.0M)(-1.00M,-22.7M)(0,0)(1.00M,22.7M)(10.0,23.0M)) *E97 99 0 VALUE { V(98)* LIMIT(((V(3)-V(4))*1.15 + -2.11),0.05,1E6)} E97 99 0 VALUE { V(98)* LIMIT(((V(3)-V(4))*1.15 + -2.11),0.00,1E6) * + LIMIT(((V(3)-V(4))*833M + -1.25),0,1)} D98 4 5 DESD D99 5 3 DESD * * Temperature / Voltage Sensitive IQuiscent R61 0 61 1 TC=3.23M,3.70U G61 3 4 61 0 1 G60 0 61 TABLE {V(3, 4)} + ((0,0)(800M,20.0U)(1.5,40.5U)(2.00,41.0U) + (3.00,41.5U)(4.00,42.0U)(5.00,43.0U)) * * Temperature Sensitive offset voltage I73 0 70 DC 1uA R74 0 70 1 TC=5.00 E75 1 71 70 0 1 * * Temp Sensistive IBias *I62 0 62 DC 1uA I62 0 62 DC 1000uA R62 0 62 REXP 724.97342U * * Temp Sensistive Offset IBias I63 0 63 DC 1uA R63 0 63 25.0 TC=12.0M,90.1U * * Models .MODEL NMI NMOS(L=2.00U W=42.0U KP=20.0U LEVEL=1 ) .MODEL DESD D N=1 IS=1.00E-15 .MODEL DN1 D IS=1P KF=50.0P AF=1 .MODEL REXP RES TCE= 557.28574M .ENDS LMV331