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NB3N502DEVB:  PLL Clock Multiplier Evaluation Board

The NB3N502 Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the performance and operation of the NB3N502 PLL Clock Multiplier. The NB3N502 is a clock multiplier device that generates a low jitter, TTL/CMOS level output clock which is a precise multiple of the external input reference clock signal source. The user's manual provides detailed information on the board's contents, layout and use, and it should be used in conjunction with the NB3N502 data sheet which contains full technical details on device specifications and operation.
特長およびアプリケーション

特長

  • Fully Assembled Evaluation Board
  • Accommodates the Electrical Characterization of the NB3N502 in the SOIC-8 Package
  • Supports the Use of a 5 MHz to 27 MHz Through-hole or Surface Mount Crystal
  • SMA Connectors are Provided for Auxiliary Input and Output Interfaces
  • Incorporates Onboard Slide Switch Controlled Multiplier Select Pins, Minimizing Excess Cabling
評価/開発ツール情報
製品 状態 Compliance 簡単な説明 使用パーツ アクション
NB3N502DEVB Active
PLL Clock Multiplier Evaluation Board NB3N502DG NB3N502DR2G
技術文書
タイプ ドキュメント・タイトル ドキュメント ID/サイズ 修正
Eval Board: Manual NB3N502DEVB Evaluation Board User's Manual EVBUM2064/D - 247.0 KB  1 
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