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MC10E196: 5.0 V ECL Programmable Delay Chip

Datasheet: 5V ECL Programmable Delay Chip
Rev. 8 (158.0kB)
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Product Overview
製品説明
The MC10E/100E196 is a programmable delay chip (PDC) designed primarily for very accurate differential ECL input edge placement applications.

The delay section consists of a chain of gates and a linear ramp delay adjust organized as shown in the logic symbol. The first two delay elements feature gates that have been modified to have delays 1.25 and 1.5 times the basic gate delay of approximately 80 ps. These two elements provide the E196 with a digitally-selectable resolution of approximately 20 ps. The required device delay is selected by the seven address inputs D[0:6] which are latched on chip by a high signal on the latch enable (LEN) control.

The FTUNE input takes an analog voltage and applies it to an internal linear ramp for reducing the 20 ps resolution still further. The FTUNE input is what differentiates the E196 from the E195.

An eighth latched input, D7, is provided for cascading multiple PDC's for increased programmable range. The cascade logic allows full control of multiple PDC's, at the expense of only a single added line to the data bus for each additional PDC, without the need for any external gating.

The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

The 100 Series contains temperature compensation.
特長
 
  • 2.0ns Worst Case Delay Range
  • 20ps/Delay Step Resolution
  • Linear Input for Tighter Resolution
  • >1.0GHz Bandwidth
  • On Chip Cascade Circuitry
  • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -4.2 V to -5.7 V
  • Internal Input Pulldown Resistors
  • ESD Protection: > 1 kV HBM, > 75 V MM
  • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
  • Moisture Sensitivity Level 1
    For Additional Information, see Application Note AND8003/D
  • Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
  • Transistor Count = 425 devices
  • Pb-Free Packages are Available
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供給状況 & サンプル
製品
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内容
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梱包形態
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タイプ
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MC10E196FNG Obsolete
Pb-free
Halide free
5.0 V ECL Programmable Delay Chip PLCC-28 776-02 3 Tube 37  
MC10E196FNR2G Obsolete
Pb-free
Halide free
5.0 V ECL Programmable Delay Chip PLCC-28 776-02 3 Tape and Reel 500  
面実装デバイスためのモイスチャー・レベル(260°Cリフローでの鉛フリー測定、235°Cリフローでの鉛フリー以外測定)
マーケットリードタイム(週) : Contact Factory
マーケットリードタイム(週) : Contact Factory
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