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Document Title
Document ID/Size
Revision
Revision Date
A Comparison of the NBC12429 and MC12429 Programmable PLL Clock Synthesizers AND8120/D (34.0kB) 0 May, 2003
A Solution for Peak EMI Reduction with Spread Spectrum Clock Generators AND9015/D (689.0kB) 0
A System Designer's Guide for Building a PCIe Clock Tree while Addressing Timing Challenges AND9202/D (179kB) 1 Mar, 2015
AC Characteristics of ECL Devices AND8090/D (896.0kB) 1 Nov, 2003
Basics of Clock Jitter AND8459/D (901.0kB) 0
Board Level Application Notes for Sawn Singulated DFN and QFN Wettable Flank Packages AND9657/D (856kB) 0 Mar, 2018
Clock Generation and Clock and Data Marking and Ordering Information Guide AND8002/D (71kB) 12
Clock Management Design Using Low Skew and Low Jitter Devices TND301/D (205.0kB) 0
Designing with PECL (ECL at +5.0 V) AN1406/D (105.0kB) 2 Sep, 1999
ECL Clock Distribution Techniques AN1405/D (54.0kB) 1 May, 2000
ECLinPS Plus™ Spice Modeling Kit AND8009/D (343.0kB) 11
ECLinPS and ECLinPS Lite SPICE I/O Modeling Kit AN1503/D (120.0kB) 6
Family Characteristics for MECL 10H™ and MECL 10K™ TND309/D (248.0kB) 1
Interfacing Between LVDS and ECL AN1568/D (121.0kB) 11 Sep, 2013
Interfacing with ECLinPS AND8066/D (72kB) 3
Metastability and the ECLinPS Family AN1504/D (103.0kB) 3
NB3H5150 Crystal Oscillator Selector Guide and PCB Layout Guidelines AND9458/D (449kB) 0 Jun, 2016
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks AND8001/D (90.0kB) 0
Phase Lock Loop General Operations AND8040/D (64.0kB) 3
Storage and Handling of Drypack Surface Mount Device AND8003/D (229kB) 3 Jan, 2020
System Clock Generators AND8248/D (110.0kB) 1
Termination of ECL Logic Devices AND8020/D (176.0kB) 6
The ECL Translator Guide AN1672/D (142.0kB) 12 Mar, 2006
Thermal Analysis and Reliability of WIRE BONDED ECL AND8072/D (119.0kB) 5
Using Wire-OR Ties in ECLInPS™ Designs AN1650/D (1130.0kB) 3
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