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データシート

データシート のため  GigaComm™ (すべてを表示)

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Document Title
Document ID/Size
Revision
Revision Date
1.8 V / 2.5 V 10Gbps Equalizer Receiver with 1:6 Differential CML Outputs NB7VQ1006M/D (1256kB) 3 Aug, 2016
1.8 V / 2.5 V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer/Translator NB7V72M/D (155.0kB) 1 Oct, 2009
1.8V / 2.5V /3.3V Differential 4:1 Mux w/Input Equalizer to 1:2 CML Clock/Data Fanout / Translator NB7VQ572M/D (170.0kB) P0 Oct, 2010
1.8V / 2.5V CML 12.5 Gbps Programmable Pre-Emphasis Copper/Cable Driver with Selectable Equalizer Receiver NB7VPQ16M/D (3635.0kB) 0 Jul, 2009
1.8V / 2.5V, 10GHz /4 Clock Divider with CML Outputs NB7V33M/D (161.0kB) 2 Jan, 2010
1.8V / 2.5V, 10GHz ÷2 Clock Divider with CML Outputs NB7V32M/D (128.0kB) 5 Aug, 2010
1.8V Differential 2:1 Mux Input to 1.2V/1.8V 1:6 CML Clock/Data Fanout Buffer /Translator NB7V586M/D (134.0kB) 0 Sep, 2008
1.8V/2.5V/3.3V 8GHz /14Gbps Differential 1:4 Clock / Data CML Fanout Buffer w/ Selectable Input Equalizer NB7VQ14M/D (167.0kB) 0 Dec, 2010
2.5 V/3.3 V SiGe Differential Smart Gate with Output Level Select NB7L86A/D (389kB) 0 Dec, 2019
2.5V / 3.3V 1:8 CML Fanout NB7L1008M/D (141kB) 1 Oct, 2013
2.5V / 3.3V 1:8 LVPECL Fanout Buffer NB7L1008/D (180kB) 1 Apr, 2014
2.5V / 3.3V Differential 2 x 2 Crosspoint Switch with CML Outputs Clock/Data Buffer / Translator NB7L72M/D (85kB) 4 Jan, 2017
2.5V / 3.3V Differential 4:1 Mux Input to 1:2 LVPECL Clock/Data Fanout /Translator NB7L572/D (134.0kB) 2 Jun, 2012
2.5V/3.3V 7GHz/10Gbps Differential 1:4 LVPECL Fanout Buffer NB7L14/D (142kB) 6 Jul, 2015
Clock / Data Multiplexer / Translator, 1.8 V / 2.5 V / 3.3 V Differential 2:1, with CML Outputs NB7V58M/D (158.0kB) 0 Aug, 2009
D Flip Flop, 1.8 V / 2.5 V Differential, with Reset and CML Outputs NB7V52M/D (84kB) 4 Jul, 2014
LVPECL Clock/Data Fanout Buffer/Translator 2.5V/3.3V Differential 2:1 Mux Input to 1:6 NB7L585/D (88kB) 2 Jul, 2014
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